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PDF ADP3802AR Data sheet ( Hoja de datos )
| Número de pieza | ADP3802AR | |
| Descripción | High Frequency Switch Mode Dual Li-Ion Battery Chargers | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
Stand-Alone Li-Ion Battery Chargers
High End-of-Charge Voltage Accuracy
؎0.4% @ +25؇C
؎0.75% @ –10؇C to +70؇C
Intelligent End-of-Charge Output Signal
Pin Programmable Cell Number Select
On Chip 3.3 V LDO Regulator
Programmable Charge Current with High Side Sense
Softstart Charge Current
Undervoltage Lockout
Drives External PMOS
؎10% Adjustable End-of-Charge Voltage
Charges NiCad, NiMH (with External Controller)
PWM Oscillator Frequency:
ADP3801: 200 kHz
ADP3802: 500 kHz
APPLICATIONS
Fast Chargers
Universal Chargers
Cellular Phones
Portable Computers
Portable Instrumentation
Desktop Chargers
Personal Digital Assistants
GENERAL DESCRIPTION
The ADP3801 and ADP3802 are complete battery charging
ICs. The devices combine a high accuracy final battery voltage
control with a constant charge current control and an on-board
Low Drop-Out Regulator (LDO). The accuracy of the final
battery voltage control is guaranteed to ± 0.75% to safely charge
Li-Ion batteries. An internal multiplexer allows the alternate
charging of two separate battery stacks. The final voltage is pin
programmable to one of three Li-Ion options: 4.2 V (one Li-Ion
cell), 8.4 V (two Li-Ion cells), or 12.6 V (three Li-Ion cells).
Paired with an external microcontroller for charge termination,
the ADP3801/ADP3802 works as a fast charger for NiCad/
NiMH batteries or as a universal charger for all three battery
chemistries. In addition, a pin is provided for changing the final
battery voltage by up to ± 10% to adjust for variations in battery
chemistry from different Li-Ion manufacturers without loss of
accuracy in the final battery voltage.
High Frequency Switch Mode
Dual Li-Ion Battery Chargers
ADP3801/ADP3802
FUNCTIONAL BLOCK DIAGRAM
VCC
DRV EOC CS+ CS– A/B
VL
SD
RESET
LDO +
GATE
REFERENCE DRIVE
CURRENT
LOOP
AMP + EOC
COMPARATOR
A/B
SELECT
MUX
SHUTDOWN
UVLO
+
RESET
PWM
SD\UVLO
ADP3801/ADP3802
FINAL BATTERY
VOLTAGE
PROGRAM
(4.2, 8.4, 12.6)
VOLTAGE
LOOP
AMP
BATTERY
VOLTAGE
ADJUST
؎10%
BATA
BATB
ISET
PROG
GND
COMP
ADJ
68H
40m⍀
VIN
3.3V
VCC DRV
VL
EOC
CS+ CS–
A/B
BATA
SD
RESET
ADP3801/ADP3802
BATB
ISET
PROG
GND
COMP
ADJ
BATA
BATB
Figure 1. 4 Amp Dual Battery Charger
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1998
1 page  
Typical Performance Characteristics–ADP3801/ADP3802
100
VCC = 10V
TA = +25؇C
80
60
40
20
0
–0.5 –0.3 –0.1 0.1 0.3 0.5
–0.4 –0.2
0 0.2 0.4
0.6
VBAT ACCURACY – %
Figure 2. VBAT Accuracy Distribution
0.4
VCC = 10V
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–40 –20
0 20 40 60
TEMPERATURE – ؇C
80 100
Figure 3. VBAT Accuracy vs.
Temperature
0.3
TA = +25؇C
0.2 VBAT = 4.2V
0.1
0
–0.1
–0.2
–0.3
6
8 10 12 14 16 18 20
SUPPLY VOLTAGE – Volts
Figure 4. VBAT Accuracy vs. Supply
Voltage
15
VCC = 10V
TA = +25؇C
10
5
0
–5
–10
–15
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5
VADJ – Volts
Figure 5. VBAT Percent Change vs. VADJ
10
VCC = 10V
9
8
7
6
5
–40 –20
0 20 40 60
TEMPERATURE – ؇C
80 100
Figure 6. Overvoltage Comparator
Threshold vs. Temperature
200
VCC = 10V
195
190
185
180
–40 –20
0 20 40 60
TEMPERATURE – ؇C
80 100
Figure 7. Overcurrent Comparator
Threshold vs. Temperature
3.7
TA = +25؇C
3.6
3.5
3.4
3.3
0 1 2 3 4 5 6 7 8 9 10
LDO LOAD CURRENT – mA
Figure 8. UVLO Trip Point-Off vs.
LDO Load Current
0.3
VCC = 10V
0.2
0.1
0
–0.1
–0.2
–0.3
–40 –20
0 20 40 60
TEMPERATURE – ؇C
80 100
Figure 9. LDO Accuracy vs.
Temperature
0.2
TA = +25؇C
0.1
0
–0.1
–0.2
4
6 8 10 12 14 16 18 20
SUPPLY VOLTAGE – Volts
Figure 10. LDO Accuracy vs. Supply
Voltage
REV. 0
–5–
5 Page 
ADP3800
COMP
EOC
(a) EOC Output Terminates Charge
ADP3800
EOC
VL
100k⍀
0.1F
270⍀
2N3906
(b) EOC Turns on LED to Signal Charge Completion
ADP3800
EOC
VL
COMP
100k⍀ 10k⍀
0.1F
2N3906
20k⍀
100k⍀
270⍀
20k⍀
2N3904 ؋ 2
(c) EOC Terminates Charge and Turns on LED
ADP3800
EOC
COMP
VL RESET
100k⍀ 10k⍀
2N3906
0.1F
20k⍀
100k⍀
100k⍀
2N3904 ؋ 2
100k⍀
1F
74H73A
JQ
KQ
BATSELB*
A/B + BATSELA*
*LEVEL SHIFTED TO
TO DRIVE PMOS
(d) Flip-Flop Switches Between Batteries on EOC Signal
Figure 23. EOC Output Circuits
ADP3801/ADP3802
COMP Node
Both the current loop and the voltage loop share a common,
high impedance compensation node, labeled COMP. A series
capacitor and resistor on this node help to compensate both
loops. The resistor is included to provide a zero in the loop
response and boost phase margin.
The voltage at the COMP node determines the duty cycle of the
PWM. The threshold levels are typically 1.0 V for 0% duty cycle
and 2.0 V for 100% duty cycle, resulting in a total range of
1.0 V. When the ADP3801/ADP3802 first turns on, the COMP
capacitor is at 0.0 V. It has to charge up to at least 1.0 V before
the duty cycle rises above 0% and the pass transistor turns on.
This “soft-start” behavior is desirable to avoid undue stress on
the external components. In addition, whenever the part is
placed in Shutdown or in UVLO, the COMP capacitor is dis-
charged to ensure soft start upon recovery.
The current available to charge and discharge the COMP ca-
pacitor during normal operation is 100 µA. Thus, the slew rate
at this node is equal to 100 µA divided by the capacitor. For a
typical capacitance of 1 µF, the slew rate is 0.1 V/ms. Thus, it
takes about 10 ms before the ADP3801/ADP3802 starts to
operate from a soft-start state. This is regardless of the internal
oscillator frequency. One important note is that the COMP
node is a high impedance point. Any external resistance or leak-
age current on this node will cause an error in both the charge
current control and the final battery voltage.
Gate Drive
The ADP3801/ADP3802 gate drive is designed to provide high
transient currents to drive the pass transistor. The rise and fall
times are typically 20 ns and 200 ns respectively when driving
a 1 nF load, which is typical for a PMOSFET with RDS(ON) =
60 mΩ. Figure 15 shows the typical transient response of the
output stage driving this load from a 10 V supply.
A voltage clamp is added to limit the pull-down voltage to 7 V
below VCC. For example, if VCC is 10 V then the output will
pull down to 3 V minimum, limiting the VGS voltage applied to
the external FET.
Low Dropout Regulator and Reference
A 3.3 V LDO is used to generate a regulated supply for internal
circuitry. Additionally, the LDO can deliver up to 10 mA of
current to power external circuitry such as a microcontroller. A
1.0 µF capacitor must be placed close to the VL pin to ensure
stability of the regulator. Due to the design of the regulator,
stability is not contingent on the ESR for the output capacitor.
Many different types of capacitors can be used providing flex-
ibility and ease of design. The LDO also includes a high accu-
racy, low drift internal reference equal to half of VL to set levels
within the part. During shutdown and UVLO, both the refer-
ence and the LDO remain active.
Shutdown
The IC may be placed in shutdown at any time to stop charging
of the batteries and to conserve power. For example, to safely
switch from one battery to the next, the part should be shut
down to momentarily interrupt charging. Also, if the batteries
have completed charging or no batteries are present, then the
part may be placed in shutdown to save power. A logic low on
REV. 0
–11–
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet ADP3802AR.PDF ] | |
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