PDF ADP3522ACP-1.8 Data sheet ( Hoja de datos )

Número de pieza	ADP3522ACP-1.8
Descripción	GSM Power Management System
Fabricantes	Analog Devices
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No Preview Available ! GSM Power Management System ADP3522 FEATURES Handles all GSM Baseband Power Management 6 LDOs Optimized for Specific GSM Subsystems Li-Ion Battery Charge Function Optimized for the AD20msp430 Baseband Chipset Reduced Package Size: 5 mm ؋ 5 mm LFCSP-32 APPLICATIONS GSM/GPRS Handsets GENERAL DESCRIPTION The ADP3522 is a multifunction power system chip optimized for GSM/GPRS handsets, especially those based on the Analog Devices AD20msp430 system solution with 1.8 V digital baseband processors, such as the AD6525, AD6526, and AD6528. It contains six LDOs, one to power each of the critical GSM subblocks. Sophisticated controls are available for power- up during battery charging, keypad interface, and RTC alarm. The charge circuit maintains low current charging during the initial charge phase and provides an end of charge (EOC) signal when a Li-Ion battery is being charged. This product also meets the market trend of reduced size with a new LFCSP package. Its footprint is only 5 mm ϫ 5 mm and yet offers excellent ther- mal performance due to the exposed die attached paddle. The ADP3522 is specified over the temperature range of –20°C to +85°C. PWRONKEY ROWX PWRONIN TCXOEN SIMEN RESCAP CHRDET EOC CHGEN BATSNS ISENSE GATEIN CHRIN GATEDR FUNCTIONAL BLOCK DIAGRAM VBAT VBAT2 VRTCIN POWER-UP SEQUENCING AND PROTECTION LOGIC SIM LDO DIGITAL CORE LDO ANALOG LDO TCXO LDO MEMORY LDO RTC LDO REF BUFFER BATTERY CHARGE CONTROLLER BATTERY VOLTAGE DIVIDER ADP3522 VSIM SIMVSEL VCORE VAN VTCXO VMEM VRTC REFOUT RESET MVBAT DGND AGND REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved. 1 page ADP3522 Parameter Symbol Conditions Min Typ Max Unit BATTERY CHARGER Charger Output Voltage Load Regulation CHRDET On Threshold CHRDET Hysteresis CHRDET Off Delay4 CHRIN Supply Current Current Limit Threshold High Current Limit (UVLO Not Active) Low Current Limit (UVLO Active) ISENSE Bias Current EOC Signal Threshold EOC Reset Threshold GATEDR Transition Time GATEDR High Voltage GATEDR Low Voltage Output High Voltage (EOC, CHRDET) Output Low Voltage (EOC, CHRDET) BATSNS ⌬BATSNS CHRIN – VBAT CHRIN – ISENSE CHRIN – ISENSE VBAT tR, tF VOH VOL VOH VOL 4.35 V ≤ CHRIN ≤ 10 V3 CHGEN = Low, No Load CHRIN = 10 V CHGEN = Low, No Load 0°C < TA < 50°C CHRIN = 5 V 0 ≤ CHRIN – ISENSE < Current Limit Threshold CHGEN = Low CHRIN < VBAT CHRIN = 5 V CHRIN = 5 V DC VBAT = 3.6 V CHGEN = Low CHRIN = 5 V DC VBAT = 3.6 V CHGEN = Low 0°C < TA < 50°C VBAT = 2 V CHGEN = Low CHRIN = 5 V – 10 V CHRIN = 5 V DC VBAT > 4.0 V CHGEN = Low CHGEN = Low CHRIN = 5 V VBAT > 3.6 V CHGEN = High, CL = 2 nF CHRIN = 5 V VBAT = 3.6 V CHGEN = High GATEIN = High IOH = –1 mA CHRIN = 5 V VBAT = 3.6 V CHGEN = High GATEIN = Low IOL = 1 mA IOH = –250 µA IOL = 250 µA 4.150 4.200 4.250 4.155 4.250 V V 15 mV 30 90 150 40 6 0.6 mV mV ms/nF mA 142 160 190 mV 149 160 180 mV 20 35 mV 200 14 35 µA mV 3.82 3.96 4.10 0.1 1 V µs 4.5 V 0.5 V VMEM – 0.25 0.25 V V NOTES 1All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods. 2This feature is intended to protect against catastrophic failure of the device. Maximum allowed operating junction temperature is 125ºC. Operation beyond 125ºC could cause permanent damage to the device. 3No isolation diode is present between the charger input and the battery. 4Delay set by external capacitor on the RESCAP pin. Specifications subject to change without notice. REV. 0 –5– 5 Page ADP3522 PWRONKEY ROWX PWRONIN SIMEN TCXOEN RESCAP CHRDET EOC CHGEN GATEIN BATSNS ISENSE GATEDR CHRIN MVBAT 110k⍀ QS R 1M⍀ CHARGER DETECT Li-ION BATTERY CHARGE CONTROLLER AND ␮PROCESSOR CHARGE INTERFACE VBAT VRTCIN VBAT2 SIMVSEL UVLO DEEP DISCHARGED UVLO SIM LDO VBAT VSEL VREF OUT EN DGND OVERTEMP SHUTDOWN DIGITAL CORE LDO VBAT VREF OUT EN DGND PG ANALOG LDO VBAT VREF OUT EN AGND RESET GENERATOR TCXO LDO VBAT VREF OUT EN AGND MEMORY LDO VBAT VREF OUT EN DGND RTC LDO VBAT VREF OUT EN DGND 1.21V EN REF BUFFER AGND Figure 1. Functional Block Diagram VSIM VCORE VAN RESET VTCXO VMEM VRTC REFOUT AGND DGND REV. 0 –11– 11 Page

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