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PDF ADP3412JR Data sheet ( Hoja de datos )
| Número de pieza | ADP3412JR | |
| Descripción | Dual MOSFET Driver with Bootstrapping | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
All-In-One Synchronous Buck Driver
Bootstrapped High-Side Drive
One PWM Signal Generates Both Drives
Programmable Transition Delay
Anticross-Conduction Protection Circuitry
APPLICATIONS
Multiphase Desktop CPU Supplies
Mobile Computing CPU Core Power Converters
Single-Supply Synchronous Buck Converters
Standard-to-Synchronous Converter Adaptations
Dual MOSFET Driver
with Bootstrapping
ADP3412
FUNCTIONAL BLOCK DIAGRAM
VCC
BST
ADP3412
IN
DLY
OVERLAP
PROTECTION
CIRCUIT
DRVH
SW
DRVL
GENERAL DESCRIPTION
The ADP3412 is a dual MOSFET driver optimized for driving
two N-channel MOSFETs which are the two switches in a
nonisolated synchronous buck power converter. Each of the
drivers is capable of driving a 3000 pF load with a 20 ns propa-
gation delay and a 30 ns transition time. One of the drivers can
be bootstrapped, and is designed to handle the high-voltage
slew rate associated with “floating” high-side gate drivers. The
ADP3412 includes overlapping drive protection (ODP) to pre-
vent shoot-through current in the external MOSFETs.
ADP3412
IN
DLY
CDLY
DELAY
1V
PGND
5V
VCC
12V
D1
BST
DRVH
CBST
Q1
SW
1V
DRVL
PGND
Q2
Figure 1. General Application Circuit
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
1 page  
2V/DIV
DRVH
DRVL
IN
20ns/DIV
TIME – ns
VCC = 5V
CLOAD = 3nF
VSW = 0V
TPC 1. DRVH Fall and DRVL Rise
Times
Typical Performance Characteristics–ADP3412
2V/DIV
DRVL
DRVH
IN
20ns/DIV
TIME – ns
VCC = 5V
CLOAD = 3nF
CDLY = 20pF
TPC 2. DRVL Fall and DRVH Rise
Times
30
VCC = 5V
CLOAD = 3nF
25
RISE TIME
20
15
FALL TIME
10
5
0
0 25 50 75 85
JUNCTION TEMPERATURE – ؇C
TPC 3. DRVH Rise and Fall Times vs.
Temperature
35
VCC = 5V
30 CLOAD = 3nF
25
RISE TIME
20
FALL TIME
15
10
5
0
0 25 50 75 85
AMBIENT TEMPERATURE – ؇C
TPC 4. DRVL Rise and Fall Times vs.
Temperature
40
VCC = 5V
TA = 25؇C
30
20
DRVH
DRVL
10
0
01 2 3 4 56
CAPACITANCE – nF
TPC 5. DRVH and DRVL Rise Times
vs. Load Capacitance
35
VCC = 5V
30 TA = 25؇C
25
DRVH
20
DRVL
15
10
5
0
0 1 2 34 56
CAPACITANCE – nF
TPC 6. DRVH and DRVL Fall Times
vs. Load Capacitance
30
VCC = 5V
CLOAD = 3nF
25
tpdlDRVH
20
15
tpdlDRVL
10
5
0
0 25 50 75 100
JUNCTION TEMPERATURE – ؇C
TPC 7. Propagation Delay vs.
Temperature
125
40
VCC = 5V
35 TA = 25؇C
CLOAD = 3nF
30
25
20
15
10
5
0
0 200 400 600 800 1000 1200
IN FREQUENCY – kHz
TPC 8. Supply Current vs.
Frequency
11.0
10.5
VCC = 5V
fIN = 250kHz
CLOAD = 3nF
10.0
9.5
9.0
0
25 50 75 100
JUNCTION TEMPERATURE – ؇C
125
TPC 9. Supply Current vs.
Temperature
REV. 0
–5–
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet ADP3412JR.PDF ] | |
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