PDF ADP3410KRU Data sheet ( Hoja de datos )

Número de pieza	ADP3410KRU
Descripción	Dual MOSFET Driver with Bootstrapping
Fabricantes	Analog Devices
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No Preview Available ! a FEATURES All-In-One Synchronous Buck Driver One PWM Signal Generates Both Drives Anticross-Conduction Protection Circuitry Programmable Transition Delay Synchronous Override Control Undervoltage Lockout Programmable Overvoltage Shutdown VCC Good Signal Drives Auxiliary Circuits Shutdown Quiescent Current < 10 ␮A APPLICATIONS Mobile Computing CPU Core Power Converters Multiphase Desktop CPU Supplies Single-Supply Synchronous Buck Converters Standard-to-Synchronous Converter Adaptations Dual MOSFET Driver with Bootstrapping ADP3410 FUNCTIONAL BLOCK DIAGRAM VCC VCCGD GND ADP3410 4.4V SD IN DLY OVPSET 1.2V CONTROL AND OVERLAP VCC PROTECTION CIRCUIT VCC BST DRVH SW DRVL DRVLSD PGND SRMON GENERAL DESCRIPTION The ADP3410 is a dual MOSFET driver optimized for driving two N-channel FETs that are the two switches in the non- isolated synchronous buck power converter topology. Each of the drivers is capable of driving a 3000␣ pF load with a 20␣ ns propagation delay and a 30␣ ns transition time. One of the drivers can be bootstrapped, and is designed to handle the high-voltage slew rate associated with “ﬂoating” high-side gate drivers. The ADP3410 has several protection features: overlapping drive prevention (ODP), undervoltage lockout (UVLO) with perform- ance speciﬁed at very low VCC levels, and overvoltage protection (OVP) that can be used to monitor either the input or output. Additional features include: programmable transition delay, a synchronous drive override control pin, a synchronous drive status monitor and, in conjunction with exiting from the UVLO mode, a VCC Good (VCCGD) signal capable of driving a 10␣ mA load. The quiescent current, when the device is disabled, is less than 10 µA. 5V VBATT TO PWM CONTROLLER VCC SD VCCGD ADP3410 IN BST DRVLSD DRVH SRMON SW OVPSET DRVL DLY GND PGND Figure 1. Typical Application Circuit VOUT REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999 1 page 5V D1 ADP3410 VBATT VCC SD VCC VCCGD DLY CDLY IN VOUT Ra OVPSET Rb DRVL 10% VCC 1V DRVLSD BIAS ENABLE VCC ADP3410 UVLO 4.4V DELAY BST CBST DRVH SW Q1 1.2V VCC DRVL PGND Q2 SRMON GND Figure 2. Functional Block Diagram IN DRVLSD DRVL 0.8V tpdlDRVLSD 2.0V tpdhDRVLSD Figure 3. DRVLSD Propagation Delay REV. 0 –5– 5 Page OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 14-Lead Thin Shrink Small Outline Package (TSSOP) (RU-14) 0.201 (5.10) 0.193 (4.90) 14 1 PIN 1 0.006 (0.15) 0.002 (0.05) 8 0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25) 7 0.0433 (1.10) MAX SEATING PLANE 0.0256 (0.65) BSC 0.0118 (0.30) 0.0075 (0.19) 8؇ 0.0079 (0.20) 0؇ 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) ADP3410 REV. 0 –11– 11 Page

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