PDF ADP3401 Data sheet ( Hoja de datos )

Número de pieza	ADP3401
Descripción	GSM Power Management System
Fabricantes	Analog Devices
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No Preview Available ! a GSM Power Management System ADP3401 FEATURES Handles all GSM Baseband Power Management Functions Four LDOs Optimized for Specific GSM Subsystems Charges Li-Mn Coin Cell for Real-Time Clock Charge Pump and Logic Level Translators for 3 V and 5 V GSM SIM Modules Thermally Enhanced 6.1 mm 28-Lead TSSOP Package APPLICATIONS GSM/DCS/PCS Handsets TeleMatic Systems ICO/Iridium Terminals GENERAL DESCRIPTION The ADP3401 is a multifunction power management system IC optimized for GSM cell phones. The wide input voltage range of 3.0 V to 7.0 V makes the ADP3401 ideal for both single cell Li-Ion and three cell NiMH designs. The current consumption of the ADP3401 has been optimized for maximum battery life, featuring a ground current of only 150 µA when the phone is in standby (digital LDO, and SIM card supply active). An undervoltage lock- out (UVLO) prevents the startup when there is not enough energy in the battery. All four integrated LDOs are optimized to power one of the critical sub-blocks of the phone. Their novel anyCAP™ architecture requires only very small output capacitors for stability, and the LDOs are insensitive to the capacitors’ equivalent series resistance (ESR). This makes them stable with any capacitor, including ceramic (MLCC) types for space-restricted applications. A step-up converter is implemented to supply both the SIM module and the level translation circuitry to adapt logic signals for 3 V and 5 V SIM modules. Sophisticated controls are avail- able for power-up during battery charging, keypad interface, and charging of an auxiliary backup battery for the real-time clock. These allow an easy interface between ADP3401, GSM proces- sor, charger, and keypad. The 28-lead TSSOP package has been thermally enhanced to maximize power dissipation capability. Furthermore, a reset circuit and a thermal shutdown function have been implemented to support reliable system design. FUNCTIONAL BLOCK DIAGRAM VBAT ADP3401 DIGITAL LDO PWRONKEY ROWX PWRONIN ANALOGON RESCAP CHRON SIMBAT CAP+ CAP؊ SIMPROG SIMON SIMGND RESETIN CLKIN DATAIO POWER-UP SEQUENCING AND PROTECTION LOGIC RTC LDO XTAL OSC LDO ANALOG LDO CHARGE PUMP LOGIC LEVEL TRANSLATION REF + BUFFER I/O CLK RST VCC RESET VRTC VTCXO VCCA VSIM REFOUT DGND AGND anyCAP is a trademark of Analog Devices, Inc. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000 1 page ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin with Respect to Any GND Pin . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +10 V Voltage on Any Pin May Not Exceed VBAT, with the Following Exceptions: VRTC, VSIM, CAP+, PWRONIN, I/O, CLK, RST Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Operating Temperature Range . . . . . . . . . . . –20°C to +85°C Maximum Junction Temperature . . . . . . . . . . . . . . . . . 125°C θJA, Thermal Impedance (TSSOP-28) . . 2-Layer Board 90°C/W θJA, Thermal Impedance (TSSOP-28) . . 4-Layer Board 60°C/W Lead Temperature Range (Soldering, 60 sec) . . . . . . . . 300°C *This is a stress rating only, operation beyond these limits can cause the device to be permanently damaged. PIN CONFIGURATION VBAT 1 28 AGND VCC 2 27 VCCA PWRONKEY 3 26 REFOUT ANALOGON 4 25 RESET PWRONIN 5 24 VTCXO ROWX 6 23 DGND CHRON 7 22 RESCAP ADP3401 VRTC 8 21 CAP+ CAP؊ 9 20 VSIM SIMBAT 10 19 CLK DATAIO 11 18 SIMON RESETIN 12 17 SIMPROG CLKIN 13 16 RST SIMGND 14 15 I/O ORDERING GUIDE Model Temperature Package Range Description Package Option ADP3401ARU –20°C to +85°C 28-Lead TSSOP RU-28A Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 ADP3401 PIN FUNCTION DESCRIPTIONS Mnemonic VBAT VCC PWRONKEY ANALOGON PWRONIN ROWX CHRON VRTC CAP– SIMBAT DATAIO RESETIN CLKIN SIMGND I/O RST SIMPROG SIMON CLK VSIM CAP+ RESCAP DGND VTCXO RESET REFOUT VCCA AGND Function Battery Input Voltage Digital Low Dropout Regulator Power On/Off Key VTCXO Enable Power On/Off Signal from Microprocessor Microprocessor Keyboard Output Charger On/Off Input Real-Time Clock Supply/Coin Cell Battery Charger Negative Side of Boost Capacitor Battery Input for the SIM Charge Pump Non-Level-Shifted Bidirectional Data I/O Non-Level-Shifted SIM Reset Non-Level-Shifted Clock Charge Pump Ground Level-Shifted Bidirectional SIM Data Input/Output Level-Shifted SIM Reset VSIM Programming: Low = 3 V, High = 5 V VSIM Enable Level-Shifted SIM Clock SIM Supply Positive Side of Boost Capacitor Reset Delay Timing Cap Digital Ground Crystal Oscillator Low Dropout Regulator Main Reset Reference Output Analog Low Dropout Regulator Analog Ground CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADP3401 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE REV. 0 –5– 5 Page ADP3401 RESETIN CLKIN ADP3401 VCC VSIM LEVEL SHIFT VCC VCC LEVEL SHIFT VSIM VSIM RST CLK DATAIO I/O Figure 19. Schematic for Level Translators Power-On/-Off ADP3401 handles all issues regarding power-on/-off of the hand- set. It is possible to turn on the ADP3401 in three different ways: • Pulling PWRONKEY low • Pulling PWRONIN high • CHRON exceeds threshold Pulling PWRONKEY key low is the normal way of turning on the handset. This will turn on all the LDOs as long as PWRONKEY is held low. The microprocessor then starts and pulls PWRONIN high after which PWRONKEY can be released. PWRONIN going high will also turn on the handset. This is the case when the alarm in the RTC module expires. An external charger can also turn on the phone. The turn-on threshold and hysteresis can be programmed via external resistors to allow full flexibility with any external charger and battery chem- istry. These resistors are referred to as R1 and R2 in Figure 15. Undervoltage Lockout (ULVO) The UVLO function in the ADP3401 prevents startup when the initial voltage of the main battery is below the 3.0 V threshold. If the battery is this low with no load, there will be little or no capacity left. When the battery is greater than 3.0 V, as with the insertion of a fresh battery, the UVLO comparator trips, the RTC LDO is enabled, and the threshold is reduced to 2.9 V. This allows the handset to start normally until the battery volt- age decays to 2.9 V open circuit. Once the 3.0 V threshold is exceeded, the RTC LDO is enabled. If, however, the backup coin cell is not connected, or is damaged or discharged below 1.5 V, the RTC LDO will not start on its own. In this situation, the RTC LDO will be started by enabling the VCC LDO. Once the system is started, i.e., the phone is turned on and the VCC LDO is up and running, the UVLO function is entirely disabled. The ADP3401 is then allowed to run down to very low battery voltages, typically around 2 V. The battery voltage is normally monitored by the microprocessor and usually shuts the phone off at around 3.0 V. If the phone is off, i.e., the VCC LDO is off, and the battery voltage drops below 2.9 V, the UVLO circuit disables startup and the RTC LDO. This is implemented with very low quies- cent current, typically 3 µA, to protect the main battery against any damage. NiMH batteries can reverse polarity if the 3-cell battery voltage drops below 3.0 V and a current of more than about 40 µA continues to flow. Lithium ion batteries will lose their capacity, although the built-in safety circuits normally present in these cells will most likely prevent any damage. RESET ADP3401 contains reset circuitry that is active both at power-up and at power-down. RESET is held low at power-up. An inter- nal power-good signal starts the reset delay. The delay is set by an external capacitor on RESCAP: tRESET = 1.0 ms nF × CRESCAP A 100 nF capacitor will produce a 100 ms reset time. At power-off, RESET will be kept low to prevent any spurious microprocessor starts. The current capability of RESET is low (a few hundred nA) when VCC is off, to minimize power consumption. Therefore, RESET should only be used to drive a single CMOS input. When VCC is on, RESET will drive about 15 µA. Overtemperature Protection The maximum die temperature for ADP3401 is 125°C. If the die temperature exceeds 160°C, the ADP3401 will disable all the LDOs except the RTC LDO, which has very limited current capa- bilities. The LDOs will not be re-enabled before the die tempera- ture is below 125°C, regardless of the state of PWRONKEY, PWRONIN, and CHRON. This ensures that the handset will always power-off before the ADP3401 exceeds its absolute maxi- mum thermal ratings. APPLICATIONS INFORMATION Input Capacitor Selection For the input voltage, VBAT, of the ADP3401, a local bypass capacitor is recommended. Use a 5 µF to 10 µF, low ESR capaci- tor. Multilayer ceramic chip capacitors provide the best combina- tion of low ESR and small size, but may not be cost-effective. A lower cost alternative may be to use a 5 µF to 10 µF tantalum capacitor with a small (1 µF to 2 µF) ceramic in parallel. LDO Capacitor Selection The performance of any LDO is a function of the output capaci- tor. The digital and analog LDOs require a 2.2 µF capacitor and the TCXO LDO requires a 0.22 µF capacitor. Larger values may be used, but the overshoot at startup will increase slightly. If a larger output capacitor is desired, be sure to check that the overshoot and settling time are acceptable for the application. All the LDOs are stable with a wide range of capacitor types and ESR due to Analog Devices’ anyCAP technology. The ADP3401 is stable with extremely low ESR capacitors (ESR ~ 0), such as multilayer ceramic capacitors, but care should be taken in their selection. Note that the capacitance of some capacitor types shows wide variations over temperature or with dc voltage. A good quality dielectric, X7R or better, is recommended. The RTC LDO has a rechargeable coin cell or an electric double- layer capacitor as a load, but an additional 0.1 µF ceramic capaci- tor is recommended for stability and best performance. Charge Pump Capacitor Selection For the input (SIMBAT) and output (VSIM) of the SIM charge pump, use 10 µF low ESR capacitors. The use of low ESR capaci- tors improves the noise and efficiency of the SIM charge pump. Multilayer ceramic chip capacitors provide the best combination of low ESR and small size but may not be cost-effective. A lower cost alternative may be to use a 10 µF tantalum capacitor with a small (1 µF to 2 µF) ceramic capacitor in parallel. REV. 0 –11– 11 Page

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