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PDF ADP3330 Data sheet ( Hoja de datos )
| Número de pieza | ADP3330 | |
| Descripción | Low Dropout Regulator | |
| Fabricantes | Analog Devices | |
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Data Sheet
High Accuracy, Ultralow IQ, 200 mA,
SOT-23, anyCAP Low Dropout Regulator
ADP3330
FEATURES
High accuracy over line and load
±0.7% at +25°C
±1.4% over temperature
Ultralow dropout voltage: 140 mV (typical) at 200 mA
Requires only COUT= 0.47 μF for stability
anyCAP = stable with any type of capacitor, including
multilayer ceramic capacitors (MLCC)
Current and thermal limiting
Low noise
Low shutdown current: <2 µA
2.9 V to 12 V supply range
–40°C to +85°C ambient temperature range
Ultrasmall, thermally enhanced, chip-on-lead™ 6-lead SOT-23
package
APPLICATIONS
Cell phones
Notebook and palmtop computers
Battery-powered systems
PCMCIA regulators
Bar code scanners
Camcorders and cameras
GENERAL DESCRIPTION
The ADP3330 is a member of the Analog Devices, Inc., precision
low dropout (LDO) anyCAP® voltage regulator family of products.
The ADP3330 operates with an input voltage range of 2.9 V to
12 V and delivers a load current up to 200 mA. The ADP3330
stands out from the conventional LDOs with a novel architecture
and an enhanced process that enables it to offer performance
advantages and higher output current than its competition. Its
patented design requires only a minimum output capacitor of
0.47 µF for stability. This device is insensitive to output capacitor
equivalent series resistance (ESR), and is stable with any good
quality capacitor, including ceramic (MLCC) types for space
restricted applications. The ADP3330 achieves exceptional
accuracy of ±0.7% at room temperature and ±1.4% over
temperature, line and load variations. The dropout voltage of
the ADP3330 is only 140 mV (typical) at 200 mA. This device also
includes a safety current limit, thermal overload protection, and
a shutdown feature. In shutdown mode, the ground current is
SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM
IN 2
ERR 3
THERMAL
PROTECTION
Q1
CC
DRIVER
SD 6
ADP3330
1 OUT
R1
gm
BAND GAP
REF
R2
4
GND
Figure 1.
reduced to less than 2 µA. The ADP3330 has an ultralow
ground current 34 µA (typical) in light load situations.
The 6-lead SOT-23 package has been thermally enhanced using
Analog Devices proprietary chip-on-lead feature to maximize
power dissipation.
VIN
CIN
0.47µF
+
–
ERR NR
ADP3330
IN OUT
SD GND
VOUT
+ COUT
– 0.47µF
ON
OFF
Figure 2. Typical Application Circuit
Rev. C
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©1999–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
ADP3330
Data Sheet
ADP3330-2.5
At TA = −40°C to +85°C, VIN = 7 V, CIN = 0.47 µF, COUT = 0.47 µF, unless otherwise noted. Ambient temperature of +85°C corresponds to a
junction temperature of +125°C under typical full load test conditions. Application stable with no load.
Table 2.
Parameter
OUTPUT VOLTAGE ACCURACY
LINE REGULATION
LOAD REGULATION
GROUND CURRENT
GROUND CURRENT IN DROPOUT
DROPOUT VOLTAGE
PEAK LOAD CURRENT
OUTPUT NOISE2
SHUTDOWN THRESHOLD
SHUTDOWN PIN INPUT CURRENT
GROUND CURRENT IN SHUTDOWN MODE
OUTPUT CURRENT IN SHUTDOWN MODE
ERROR PIN OUTPUT LEAKAGE
ERROR PIN OUTPUT LOW VOLTAGE
Symbol
VOUT
ΔVO/ΔVIN
ΔVO/ΔIL
IGND
IGND
VDROP
ILDPK
VNOISE
VTHSD
ISD
IGNDSD
IOSD
IEL
VEOL
Test Conditions/Conditions
VIN = 2.9 V to 12 V,
IL = 0.1 mA to 200 mA, TA = 25°C
VIN = 2.9 V to 12 V, IL = 0.1 mA to
150 mA, TA = −40°C to +85°C
VIN = 2.9 V to 12 V, IL = 0.1 mA to
200 mA, TA = −20°C to +85°C
VIN = 2.9 V to 12 V, TA = 25°C
IL = 0.1 mA to 200 mA, TA = 25°C
IL = 200 mA, TA = −20°C to +85°C
IL = 150 mA
IL = 50 mA
IL = 0.1 mA
VIN = VOUTNOM − 100 mV, IL = 0.1 mA
VOUT = 98% of VOUTNOM
IL = 200 mA, TA = −20°C to +85°C
IL = 150 mA
IL = 10 mA
IL = 1 mA
VIN = VOUTNOM + 1 V
f = 10 Hz to 100 kHz, CL = 10 µF,
IL = 200 mA, CNR = 10 nF, VOUT = 3 V
f = 10 Hz to 100 kHz, CL = 10 µF,
IL = 200 mA, CNR = 0 nF, VOUT = 3 V
On
Off
VIN = 12 V, 0 V<SD ≤12 V
0 V <SD ≤5 V
SD = 0 V, VIN = 12 V
TA = 25°C at VIN = 12 V
TA = 85°C at VIN = 12 V
VEO = 5 V
ISINK = 400 µA
Min Typ
−0.7
−1.4
−1.4
0.04
0.04
1.6
1.2
0.4
34
37
140
110
42
25
300
47
95
2.0
1.9
1.4
0.01
0.19
Max Unit
+0.7 %
+1.4 %
+1.4 %
mV/V
mV/mA
4.0 mA
3.1 mA
1.1 mA
50 µA
55 µA
230 mV
170 mV
60 mV
501 mV
mA
µV rms
µV rms
V
0.4 V
9 µA
6 µA
2 µA
1 µA
2 µA
1 µA
0.40 V
1 Application stable with no load.
2 See Figure 21 and Applications Information section for additional information.
Rev. C | Page 4 of 16
5 Page 
ADP3330
THEORY OF OPERATION
The anyCAP low dropout (LDO) ADP3330 uses a single control
loop for regulation and reference functions. The output voltage
is sensed by a resistive voltage divider consisting of R1 and R2,
which is varied to provide the available output voltage options.
Feedback is taken from this network by way of a series diode
(D1) and a second resistor divider (R3 and R4) to the input of
an amplifier.
INPUT
OUTPUT
Q1
COMPENSATION
CAPACITOR
ATTENUATION R1
(VBAND GAP/VOUT)
NONINVERTING
WIDEBAND
PTAT
gm VOS
R3 D1
(a)
DRIVER
PTAT
ADP3330
R4
CURRENT
R2
CLOAD
RLOAD
GND
Figure 22. Functional Block Diagram
A very high gain error amplifier is used to control this loop. The
amplifier is constructed in such a way that, at equilibrium, the
amplifier produces a large, temperature proportional input
offset voltage that is repeatable and very well controlled. The
temperature proportional offset voltage is combined with the
complementary diode voltage to form a virtual band gap
voltage, implicit in the network, although it never appears
explicitly in the circuit. Ultimately, this patented design makes it
possible to control the loop with only one amplifier. This
technique also improves the noise characteristics of the
amplifier by providing more flexibility on the trade-off of noise
sources that leads to a low noise design.
The R1, R2 divider is chosen in the same ratio as the band gap
voltage to the output voltage. Although the R1, R2 resistor
divider is loaded by the D1 diode and a second divider
consisting of R3 and R4, the values are chosen to produce a
temperature stable output. This unique arrangement specifically
corrects the loading of the divider so that the typical error
resulting from base current loading in conventional circuits is
avoided.
Data Sheet
The patented amplifier controls a new and unique noninverting
driver that drives the pass transistor, Q1. The use of this
noninverting driver enables the frequency compensation to
include the load capacitor in a pole splitting arrangement to
achieve reduced sensitivity to the value, type, and ESR of the
load capacitance.
Most LDOs place strict requirements on the range of ESR values
for the output capacitor because they are difficult to stabilize,
due to the uncertainty of load capacitance and resistance.
Moreover, the ESR value required to keep conventional LDOs
stable changes depending on load and temperature. These ESR
limitations make designing with LDOs more difficult because of
their unclear specifications and extreme variations over
temperature.
The ADP3330 anyCAP LDO overcomes these limitations. It can
be used with virtually any good quality capacitor, with no
constraint on the minimum ESR. The innovative design allows
the circuit to be stable with just a small 0.47 µF capacitor on the
output. Additional advantages of the pole splitting scheme
include superior line noise rejection and very high regulator
gain, which leads to excellent line and load regulation. An
impressive ±1.4% accuracy is guaranteed over line, load and
temperature.
Additional features of the circuit include current limit, thermal
shutdown, and noise reduction. Compared to standard
solutions that give warning after the output has lost regulation,
the ADP3330 provides improved system performance by
enabling the ERR pin to give warning just before the device
loses regulation.
When the temperature of the chip rises to more than 165°C, the
circuit activates a soft thermal shutdown, indicated by a signal
low on the ERR pin, to reduce the current to a safe level.
Rev. C | Page 10 of 16
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet ADP3330.PDF ] | |
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