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ADP3204JCP-REEL Datasheet دیتاشیت PDF دانلود

دیتاشیت - Analog Devices - 3-Phase IMVP-II and IMVP-III Core Controller for Mobile CPUs

شماره قطعه ADP3204JCP-REEL
شرح مفصل 3-Phase IMVP-II and IMVP-III Core Controller for Mobile CPUs
تولید کننده Analog Devices 
آرم Analog Devices 


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ADP3204JCP-REEL شرح
a
3-Phase IMVP-II and IMVP-III
Core Controller for Mobile CPUs
ADP3204*
FEATURES
Pin Selectable 1-, 2-, or 3-Phase Operation
Static and Dynamic Current Sharing Characteristics
Backward Compatible to IMVP-II
Superior Load Transient Response with ADOPT®
Analog Devices’ Optimal Positioning Technology
Noise-Blanking for Speed and Stability
Synchronous Rectifier Control Extends Battery Life
Smooth Output Transition During VID Code Change
Cycle-by-Cycle Current Limiting
Hiccup or Latched Overload Protection
Transient-Glitch-Free Power Good
Soft Start Eliminates Power-On In-Rush Current Surge
Two-Level Overvoltage and Reverse Voltage
Protection
APPLICATIONS
IMVP-II and IMVP-III Core DC-to-DC Converters
Fixed Voltage Mobile CPU Core DC-to-DC Converters
Notebook/Laptop Power Supplies
Programmable Output Power Supplies
GENERAL DESCRIPTION
The ADP3204 is a 1-, 2-, or 3-phase hysteretic peak current
dc-to-dc buck converter controller dedicated to power a mobile
processor’s core. The optimized low voltage design is powered
from the 3.3 V system supply. The nominal output voltage is
set by a 5-bit VID code. To accommodate the transition time
required by the newest processors, the ADP3204 features
high speed operation to allow a minimized inductor size that
results in the fastest change of current to the output. To
further allow for the minimum number of output capacitors
to be used, the ADP3204 features active voltage positioning
with ADOPT optimal compensation to ensure a superior
load transient response. The output signals interface with a
maximum of three ADP3415 MOSFET drivers that are
optimized for high speed and high efficiency for driving both the
top and bottom MOSFETs of the buck converter. The
ADP3204 is capable of controlling the synchronous rectifiers to
extend battery lifetime in light load conditions.
HYSSET
DSHIFT
BSHIFT
DPRSHIFT
FUNCTIONAL BLOCK DIAGRAM
ADP3204
BOM
DPSLP
DPRSLP
VCC
HYSTERESIS
SETTING
AND
SHIFT-MUX
VR
PHASE
SPLITTER
VID4
VID3
VID2
VID1
VID0
BOM
DPSLP
DPRSLP
PWRGD
SD
CLIM
EN
CORE
CURRENT
SENSE
MUX
DPRSLP
VID
GEN
VID
MUX
AND
REG
5-BIT VID
DAC
AND
FIXED
REF
VR
VID TRANSIENT
DETECTOR AND
SHIFT SELECTOR
COREGD MONITOR
SS-HICCUP TIMER
AND OCP
PWRGD BLANKER
SR CONTROL
ENABLE UVLO-MAIN BIAS OVP AND RVP
PM MODULE
GND
OUT3
OUT2
OUT1
CS3
CS2
CS1
CS+
CS–
RAMP
REG
DACOUT
DACRAMP
COREFB
SS
DRVLSD
CLAMP
ADOPT is a trademark of Analog Devices, Inc.
*Protected by U.S.Patent No. 5,969,657; other patents pending.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002

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