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PDF ADP3203 Data sheet ( Hoja de datos )
| Número de pieza | ADP3203 | |
| Descripción | 2-Phase IMVP-II & IMVP-III Core Controller for Mobile CPUs | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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PRELIMINARY TECHNICAL DATA
a
2-Phase IMVP-II & IMVP-III
Core Controller for Mobile CPUs
Preliminary Technical Data
FEATURES
Pin Selectable 1 or 2-Phase Operation
Backward Compatible to IMVP-II
Excellent Static and Dynamic Current Sharing
Superior Load Transient Response with ADOPTTM
Optimal Positioning Technology
Noise-Blanking for Speed and Stability
Synchronous Rectifier Control for Extended Battery
Life
Cycle-by-Cycle Current Limiting
Hiccup or Latched Overload Protection
Transient-Glitch-Free Power Good
Soft Start Eliminates Power-On In-Rush Current Surge
Two-Level Over-Voltage and Reverse-Voltage
Protection
APPLICATIONS
IMVP II-III Core DC/DC Converters
Fixed Voltage Mobile CPU Core DC/DC Converters
Notebook/Laptop Power Supplies
Programmable Output Power Supplies
GENERAL DESCRIPTION
The ADP3203 is a 1 or 2-phase hysteretic peak current
DC-DC buck converter controller dedicated to power a
mobile processor's core. The optimized low voltage design is
powered from the 3.3 V system supply and draws only
10 µA maximum in shutdown. The nominal output voltage
is set by a 5-bit VID code. To accommodate the transition
time required by the newest processors for on-the-fly VID
changes, the ADP3203 features high-speed operation to
allow a minimized inductor size that results in the fastest
change of current to the output. To further allow for the
minimum number of output capacitors to be used, the
ADP3203 features active voltage positioning with ADOPTTM
optimal compensation to ensure a superior load transient
response. The output signal interfaces with the ADP3415
MOSFET driver that is optimized for high speed and high
efficiency for driving both the top and bottom MOSFETs of
the buck converter. The ADP3203 is capable of controlling
the synchronous rectifier to extend battery lifetime in light
load conditions.
ADP3203
FUNCTIONAL BLOCK DIAGRAM
ADP3203
HYSSET 1
DSHIFT 2
BSHIFT 3
VCC
24
HYSTERESIS
SETTING
&
SHIFT-MUX
VR
VID4 4
VID3 5
VID2 6
VID1 7
VID0 8
SD 13
PWRGD 12
DPRSLP 11
DSLP 10
BOM 9
CLIM
EN
CORE
PHASE
SPLITER
CURRENT
SENSE
MUX
5-BIT VID
DAC
&
FIXED
REF
VR
ENABLE _UVLO MAIN BIAS SR CONTROL
PWRGD BLANKER
COREGD MONITOR
VID MUX &
SHIFT
SELECTOR
SS-HICCUP TIMER & OCP
OVP & RVP
PM MODULE
19
GND
21 OUT2
20 OUT1
23 CS2
22 CS1
27 CS+
28 CS-
25 RAMP
26 REG
18 DACOUT
15 DRVLSD
17 COREFB
16 SS
14 CLAMP
REV. PrD 1/02
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel:781/329-4700
www.analog.com
Fax:781/326-8703
©ANALOG DEVICES, INC., 2002
1 page  
PRELIMINARY TECHNICAL DATction Description
ADP3203
Pin Mnemonic
1 HYSSET
2 DSHIFT
3 BSHIFT
4–8 VID[4:0]
9 BOM
10 DSLP
11 DPRSLP
PIN FUNCTION DESCRIPTIONS
Function
Hysteresis Set. This is an analog I/O pin whose output is a fixed voltage reference and whose input
is a current that is programmed by an external resistance to ground. The current is used in the IC
to set the hysteretic currents for the Core Comparator and the Current Limit Comparator.
Modification of the resistance will affect both the hysteresis of the feedback regulation and the
current limit set point and hysteresis.
Deep Sleep Shift. This is an analog I/O pin whose output is the VID reference voltage and whose
input is a current that is programmed by an external resistance to ground. The current is used in
the IC to set a switched bias current out of the RAMP pin, depending on whether it is activated by
the DSLP# signal. When activated, this added bias current creates a downward shift of the
regulated core voltage to a predetermined optimum level for regulation corresponding to Deep
Sleep mode of CPU operation. The use of the VID code as the reference makes the Deep Sleep
offset a fixed percentage of the VID setting, as required by specifications.
Battery Optimized Mode (BOM) Shift. This is an analog I/O pin whose output that is the VID
reference voltage and whose input current is programmed by an external resistance to ground. The
current is used in the IC to set a switched bias current out of the RAMP pin, depending on
whether it is activated by the BOM signal. When activated, this added bias current creates a
downward shift of the regulated core voltage to a predetermined optimum level for regulation
corresponding to Battery Optimized Mode of CPU operation. The use of the VID code as the
reference makes the DSHIFT a fixed percentage of the VID setting, as required by specifications.
Voltage Identification Inputs. These are the VID inputs for logic control of the programmed
reference voltage that appears at the DACOUT pin, and, via external component configuration, is
used for setting the output voltage regulation point. The VID pins have a specified internal pullup
current such that, if left open, the pins will default to a logic high state. The VID code does not set
the DAC output voltage directly but through a transparent latch which is clocked by the BOM
pin's GMUXSEL signal rising and falling edge.
Battery Optimized Mode Control (active low). This is a digital input pin that corresponds to the
system's GMUXSEL signal that corresponds to Battery Optimized Mode of the CPU operation in
its active low state and Performance Optimized Mode (POM) in its deactivated high state. The
signal also controls the optimal positioning of the core voltage regulation level by offsetting it
downwards in Battery Optimized Mode according to the functionality of the BSHIFT and RAMP
pins. It is also used to initiate a masking period for the PWRGD signal whenever a GMUXSEL
signal transition occurs.
Deep Sleep Mode Control (active low). This is a digital input pin corresponding to the system's
STP CPU signal which, in its active state, corresponds to Deep Sleep mode of the CPU operation,
which is a subset operating mode of either BOM or POM operation. The signal controls the
optimal positioning of the core voltage regulation level by offsetting it downwards according to the
functionality of the DSHIFT and RAMP pins.
Deeper Sleep Mode Control (active high). This is a digital input pin corresponding to the system's
DPRSLPVR signal corresponding to Deeper Sleep mode of the CPU operation. The signal when
it is activated controls the DAC output voltage by disconnecting the VID signals from the DAC
input and setting a specified internal Deeper Sleep code instead. At de-assertion of the
DPRSLPVR signal, the DAC output voltage returns to the voltage level determined by the
external VID code. The DPRSLPVR signal is also used to initiate a blanking period for the
PWRGD signal to disable its response to a pending dynamic core voltage change corresponds to
the VID code transition.
REV. PrD
–5–
5 Page 
PRELIMINARY TECHNICAL DATA
ADP3203
near the MOSFETs will help. Even just small airflow
can help tremendously. Paralleled MOSFETs to achieve
a given resistance will help spread the heat.
6. An external "antiparallel" schottky diode (across the
bottom MOSFET) may help efficiency a small amount
(< ~1 %) depending on its forward voltage drop com-
pared to the MOSFET's body diode at a given current; a
MOSFET with a built in antiparallel schottky is more
effective. For an external schottky, it should be placed
next to the bottom MOSFET or it may not be effective
at all.
7. The VCC bypass capacitor should be close to the VCC
pin and connected on either a very short trace to the
GND pin or to the GND plane.
Output Filter
Output Inductor and Capacitors, Current Sense Resistor
8. Locate the current sense resistors very near to the output
voltage plane.
9. The load-side heads of two sense resistors should join as
closely as possible for accurate current signal measure-
ment of each phase.
10. PCB trace resistances from the current sense resistors to
the regulation point should be minimized, known
(calculated or measured), and compensated for as part
of the design if it is significant. (Remote sensing is not
sufficient for relieving this requirement!) A square
section of 1-ounce copper trace has a resistance of
~500 mΩ and this adds to the specified DC output
resistance of the power converter. The output capaci-
tors should similarly be close to the regulation point and
well tied into power planes as impedance here will add
to the "AC output resistance" (i.e., the ESR) that is
implicitly specified as well.
11. Whenever high currents must be routed between PCB
layers, vias should be used liberally to create parallel
current paths so that the resistance and inductance is
minimized and the via current rating is not exceeded.
Control Circuitry
ADP3203, Control Components
12. If the ADP3203 cannot be placed as previously recom-
mended, at the least care should be taken to keep the
device and surrounding components away from radia-
tion sources (e.g., from power inductors) and capacitive
coupling from noisy power nodes.
13. Noise immunity can be improved by the use of a
devoted signal ground plane for the power controller
and its surrounding components. Space for a ground
plane might readily be available on a signal plane of the
PCB since it is often unused in the vicinity of the power
controller.
14. If critical signal lines (i.e., signals from the current sense
resistor leading back to the ADP3203) must cross
through power circuitry, it is best if a signal ground
plane can be interposed between those signal lines and
the traces of the power circuitry. This serves as a shield
to minimize noise injection into the signals.
15. Absolutely avoid crossing any signal lines over the
switching power path loop, described previously.
16. Accurate voltage positioning depends on accurate
current sensing, so the control signals which monitor the
voltage differentially across the current sense resistor
should be kelvin connected. Please refer to ADI Evalua-
tion Board of the ADP3203 and its documentation for
control signal connection with sense resistors.
17. The RC filter used for the current sense signal should be
located near the control components as this serves the
dual purpose of filtering out the effect of the current
sense resistors' parasitic inductance and noise picked up
along the routing of the signal. The former purpose is
achieved by having the time constant of the RC filters
approximately matched to that of the sense resistors and
is important for maintaining the accuracy of the current
signal.
VID4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
VID3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
TABLE 1. VID CODE
VID2 VID1 VID0
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
VOUT
1.750
1.700
1.650
1.600
1.550
1.500
1.450
1.400
1.350
1.300
1.250
1.200
1.150
1.100
1.050
1.00
0.975
0.950
0.925
0.900
0.875
0.850
0.825
0.800
0.775
0.750
0.725
0.700
0.675
0.650
0.625
0.600
REV. PrD
–11–
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet ADP3203.PDF ] | |
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