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PDF ADP3179 Data sheet ( Hoja de datos )
| Número de pieza | ADP3179 | |
| Descripción | 4-Bit Programmable Synchronous Buck Controllers | |
| Fabricantes | Analog Devices | |
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FEATURES
Optimally Compensated Active Voltage Positioning
with Gain and Offset Adjustment (ADOPT™) for
Superior Load Transient Response
Complies with VRM 8.4 Specifications with Lowest
System Cost
4-Bit Digitally Programmable 1.3 V to 2.05 V Output
N-Channel Synchronous Buck Driver
Two On-Board Linear Regulator Controllers
Total Accuracy ؎0.8% Over Temperature
High Efficiency Current-Mode Operation
Short Circuit Protection
Power Good Output
Overvoltage Protection Crowbar Protects Micro-
processors with No Additional External Components
APPLICATIONS
Core Supply Voltage Generation for:
Intel Pentium® III
Intel Celeron™
4-Bit Programmable
Synchronous Buck Controllers
ADP3159/ADP3179
FUNCTIONAL BLOCK DIAGRAM
GND
LRFB1
LRDRV1
LRFB2
LRDRV2
COMP
VCC
CT
ADP3159/ADP3179
UVLO
& BIAS
OSCILLATOR
SET
RESET
REFERENCE
CROWBAR
REF
PWM
DRIVE
VLR1
DAC+20%
VLR2
REF
DAC–20%
CMP
–+
gm
VID DAC
DRVH
DRVL
PWRGD
CS–
CS+
FB
GENERAL DESCRIPTION
The ADP3159 and ADP3179 are highly efficient output syn-
chronous buck switching regulator controllers optimized for
converting a 5 V main supply into the core supply voltage
required by high-performance processors. These devices use an
internal 4-bit DAC to read a voltage identification (VID) code
directly from the processor, which is used to set the output
voltage between 1.3 V and 2.05 V. They use a current mode,
constant off-time architecture to drive two N-channel
MOSFETs at a programmable switching frequency that can be
optimized for regulator size and efficiency.
The ADP3159 and ADP3179 also use a unique supplemental
regulation technique called Analog Devices Optimal Position-
ing Technology (ADOPT) to enhance load transient
performance. Active voltage positioning results in a dc/dc con-
verter that meets the stringent output voltage specifications
for high-performance processors, with the minimum number
VID3 VID2 VID1 VID0
of output capacitors and smallest footprint. Unlike voltage-
mode and standard current-mode architectures, active voltage
positioning adjusts the output voltage as a function of the load
current so it is always optimally positioned for a system tran-
sient. The devices also provide accurate and reliable short
circuit protection and adjustable current limiting. They also
include an integrated overvoltage crowbar function to protect
the microprocessor from destruction in case the core supply
exceeds the nominal programmed voltage by more than 20%.
The ADP3159 and ADP3179 contain two fixed-output volt-
age linear regulator controllers that are designed to drive
external N-channel MOSFETs. The outputs are internally
fixed at 2.5 V and 1.8 V in the ADP3159, while the ADP3179
provides adjustable output, which is set using an external
resistor divider. These linear regulators are used to generate
the auxiliary voltages (AGP, GTL, etc.) required in most moth-
erboard designs, and have been designed to provide a high
bandwidth load-transient response.
The ADP3159 and ADP3179 are specified over the commercial
temperature range of 0°C to 70°C and are available in a 20-lead
TSSOP package.
ADOPT is a trademark of Analog Devices, Inc.
Pentium is a registered trademark of Intel Corporation.
Celeron is a trademark of Intel Corporation.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
1 page  
ADP3159/ADP3179
4-BIT CODE
VFB
ADP3159/
ADP3179
1 NC
GND 20
2 VID0
NC 19
3 VID1
DRVH 18
4 VID2
DRVL 17
5 VID3
VCC 16
6 PWRGD LRFB2 15
7 LRFB1 LRDRV2 14
8 LRDRV1 COMP 13
9 FB
CT 12
10 CS–
CS+ 11
+
1F
NC = NO CONNECT
1.2V
12V
100nF
100⍀
100nF
AD820
Figure 1. Closed Loop Output Voltage Accuracy
Test Circuit
VLR1
10nF
ADP3159/
ADP3179
1 NC
GND 20
2 VID0
NC 19
3 VID1
DRVH 18
4 VID2
DRVL 17
5 VID3
VCC 16
6 PWRGD LRFB2 15
7 LRFB1 LRDRV2 14
8 LRDRV1 COMP 13
9 FB
CT 12
10 CS–
CS+ 11
+
1F
VCC
100nF
VLR2
10nF
NC = NO CONNECT
Figure 2. Linear Regulator Output Voltage Accuracy
Test Circuit
THEORY OF OPERATION
The ADP3159 and ADP3179 use a current-mode, constant
off-time control technique to switch a pair of external N-channel
MOSFETs in a synchronous buck topology. Constant off-time
operation offers several performance advantages, including that no
slope compensation is required for stable operation. A unique
feature of the constant off-time control technique is that since
the off-time is fixed, the converter’s switching frequency is a
function of the ratio of input voltage to output voltage. The fixed
off-time is programmed by the value of an external capacitor
connected to the CT pin. The on-time varies in such a way
that a regulated output voltage is maintained as described below
in the cycle-by-cycle operation. The on-time does not vary under
fixed input supply conditions, and it varies only slightly as a func-
tion of load. This means that the switching frequency remains
fairly constant in a standard computer application.
Active Voltage Positioning
The output voltage is sensed at the CS– pin. A voltage error
amplifier, (gm), amplifies the difference between the output
voltage and a programmable reference voltage. The reference
voltage is programmed to between 1.3 V and 2.05 V by an inter-
nal 4-bit DAC that reads the code at the voltage identification
(VID) pins (Refer to Table I for output voltage vs. VID pin code
information). A unique supplemental regulation technique called
Analog Devices Optimal Positioning Technology (ADOPT)
adjusts the output voltage as a function of the load current so
that it is always optimally positioned for a load transient. Stan-
dard (passive) voltage positioning, sometimes recommended for
use with other architectures, has poor dynamic performance
which renders it ineffective under the stringent repetitive tran-
sient conditions specified in Intel VRM documents. Consequently,
such techniques do not allow the minimum possible number of
output capacitors to be used. ADOPT, as used in the ADP3159
and ADP3179, provides a bandwidth for transient response that
is limited only by parasitic output inductance. This yields opti-
mal load transient response with the minimum number of
output capacitors.
Cycle-by-Cycle Operation
During normal operation (when the output voltage is regulated),
the voltage error amplifier and the current comparator are the
main control elements. During the on-time of the high-side
MOSFET, the current comparator monitors the voltage between
the CS+ and CS– pins. When the voltage level between the two
pins reaches the threshold level, the DRVH output is switched to
ground, which turns off the high-side MOSFET. The timing
capacitor CT is then charged at a rate determined by the off-time
controller. While the timing capacitor is charging, the DRVL
output goes high, turning on the low-side MOSFET. When the
voltage level on the timing capacitor has charged to the upper
threshold voltage level, a comparator resets a latch. The output
of the latch forces the low-side drive output to go low and the
high-side drive output to go high. As a result, the low-side switch
is turned off and the high-side switch is turned on. The sequence
is then repeated. As the load current increases, the output volt-
age starts to decrease. This causes an increase in the output of
the voltage-error amplifier, which, in turn, leads to an increase
in the current comparator threshold, thus tracking the load current. To
prevent cross conduction of the external MOSFETs, feedback is
incorporated to sense the state of the driver output pins. Before
the low-side drive output can go high, the high-side drive output
must be low. Likewise, the high-side drive output is unable to
go high while the low-side drive output is high.
Power Good
The ADP3159 has an internal monitor that senses the output
voltage and drives the PWRGD pin of the device. This pin is an
open drain output whose high level (when connected to a pull-up
resistor) indicates that the output voltage has been within a ±20%
regulation band of the targeted value for more than 500 ms. The
PWRGD pin will go low if the output is outside the regulation
band for more than 500 ms.
Output Crowbar
An added feature of using an N-channel MOSFET as the syn-
chronous switch is the ability to crowbar the output with the same
MOSFET. If the output voltage is 20% greater than the targeted
value, the controller IC will turn on the lower MOSFET,
which will current-limit the source power supply or blow its fuse,
pull down the output voltage, and thus save the microprocessor
from destruction. The crowbar function releases at approximately
50% of the nominal output voltage. For example, if the output
is programmed to 1.5 V, but is pulled up to 1.85 V or above, the
crowbar will turn on the lower MOSFET. If in this case the output
is pulled down to less than 0.75 V, the crowbar will release,
allowing the output voltage to recover to 1.5 V if the fault
condition has been removed.
REV. A
–5–
5 Page 
ADP3159/ADP3179
Although a single termination resistor equal to RCOMP would
yield the proper voltage positioning gain, the dc biasing of that
resistor would determine how the regulation band is centered
(i.e., offset). Note that sometimes the specified regulation band
is asymmetrical with respect to the nominal VID voltage. With
the ADP3159, the offset is already considered part of the design
procedure—no special provision is required. To accomplish the
dc biasing, it is simplest to use two resistors to terminate the gm
amplifier output, with the lower resistor (RB) tied to ground and
the upper resistor (RA) to the 12 V supply of the IC. The values
of these resistors can be calculated using:
RA
=
gm
VDIV
× (VOUT (OS )
+ K)
=
12 V
2.2 mmho × (22 mV
+ 4.7 × 10–2 )
= 79.1 kΩ
(26)
where K is a constant determined by internal characteristics of
the ADP3159, peak-to-peak inductor current ripple (IRIPPLE),
and the current sampling resistor (RSENSE). K can be calculated
using Equations 28 and 29. VDIV is the resistor divider supply
voltage (e.g., the recommended 12 V supply) and VOUT(OS) is
the output voltage offset from the nominal VID-programmed
value under no load condition. This offset is given by Equation 30.
The closest 1% value for RA is 78.7 kΩ. This value is then used
to solve for RB:
RB
=
RA × RCOMP
RA – RCOMP
= 78.7 kΩ × 9.2 kΩ
78.7 kΩ – 9.2 kΩ
= 10.4 kΩ
The nearest 1% value of 10.5 kΩ was chosen for RB.
(27)
K
=
I L( RIPPLE
2
)
×
(RSENSE × nI
gm × RTOTAL
)
+
VGNL
gm × RTOTAL
– VCC
2 × gm ROGM
K
=
3.8
2
A
×
2.2
4 mΩ
mmho
×
×
25
9.1
kΩ
+ 1.174
2.2 mmho × 9.1 kΩ
− 12 V
2 × 2.2 mmho × 130 kΩ
(28)
= 4.7 × 10–2
VGNL
= VGNLO
+
I L( RIPPLE ) × RSENSE
2
× nI
−
VIN
− VVID
L
× tD
× RSENSE
×
nI
VGNL
= 1V
+
3.8
A × 4 mΩ × 25
2
−
5V –
1.5
1.7 V
µH
×
75
ns
×
4
mΩ
×
25
= 1.174 V
(29)
( )VOUT (OS ) = VOUT ( MAX ) − VVID
−
RE ( MAX )
× I L( RIPPLE )
2
− VVID
× kVID
VOUT (OS )
=
40 mV
−
5 mΩ
× 3.8
2
A
− 1.7V
× 5 × 10–3
=
22
mV
(30)
Finally, the compensating capacitance is determined from the
equality of the pole frequency of the error amplifier gain and the
zero frequency of the impedance of the output capacitor:
COC
=
COUT × ESR
RTOTAL
=
5 mF × 4.8 mΩ
9.1 kΩ
=
2.6 nF
(31)
The closest standard value for COC is 2.7 nF
Trade-Offs Between DC Load Regulation and AC Load
Regulation
Casual observation of the circuit operation—e.g., with a voltmeter
—would make it appear that the dc load regulation appears to
be rather poor compared to a conventional regulator (see Figure
4). This would be especially noticeable under very light or very
heavy loads where the voltage is “positioned” near one of the
extremes of the regulation window rather than near the nominal
center value. It must be noted and understood that this low gain
characteristic (i.e., loose dc load regulation) is inherently required
to allow improved transient containment (i.e., to achieve tighter
ac load regulation). That is, the dc load regulation is intentionally
sacrificed (but kept within specification) in order to minimize
the number of capacitors required to contain the load transients
produced by the CPU.
3.3V
ADP3159 /A DP3179
1F
VLR2
2.5V, 2.2A
RS
250m⍀
100F
1k⍀
68pF
10k⍀
LRDRV1
LRFB1
2.5V
Figure 6. Adding Overcurrent Protection to the
Linear Regulator
Linear Regulators
The two linear regulators provide a low cost, convenient and
versatile solution for generating additional supply rails. The
maximum output load current is determined by the size and
thermal impedance of the external N-channel power MOSFET
that is placed in series with the supply. The output voltage is
sensed at the LRFB pin and compared to an internal reference
voltage in a negative feedback loop which keeps the output voltage
in regulation. If the load is reduced or increased, the MOSFET
drive will also be reduced or increased by the controller IC to
provide a well-regulated ± 2.5% accurate output voltage.
The LRFB threshholds of the ADP3159 are internally set at
2.5 V(LRFB1) and 1.8 V(LRFB2), while the LRFB pins of the
ADP3179 are compared to an internal 1 V reference. This allows
the use of an external resistor divider network to program the
linear regulator output voltage. The correct resistor values for
setting the output voltage of the linear regulators in the
ADP3179 can be determined using:
VOUT(LR)
= VLRFB
×
RU + RL
RL
(32)
Assuming that RL =10 kΩ, VOUT(LR) = 1.2 V and rearranging
equation 32 to solve for RU yields:
( )RU
=
10 kΩ ×
VOUT(LR) − VLRFB
VLRFB
10 kΩ × (1.2V − 1V )
RU =
1V
= 2 kΩ
(33)
REV. A
–11–
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet ADP3179.PDF ] | |
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