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PDF ADP3162 Data sheet ( Hoja de datos )
| Número de pieza | ADP3162 | |
| Descripción | 5-Bit Programmable 2-Phase Synchronous Buck Controller | |
| Fabricantes | Analog Devices | |
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a
FEATURES
ADOPT™ Optimal Positioning Technology for Superior
Load Transient Response and Fewest Output
Capacitors
Complies with VRM 8.5 with Lowest System Cost
Active Current Balancing Between Both Output Phases
5-Bit Digitally Programmable 1.05 V to 1.825 V Output
Dual Logic-Level PWM Outputs for Interface to
External High-Power Drivers
Total Output Accuracy ؎0.8% Over Temperature
Current-Mode Operation
Short Circuit Protection
Power Good Output
Overvoltage Protection Crowbar Protects
Microprocessors with No Additional
External Components
APPLICATIONS
Desktop PC Power Supplies for:
Intel Tualatin Processors
VRM Modules
5-Bit Programmable 2-Phase
Synchronous Buck Controller
ADP3162
FUNCTIONAL BLOCK DIAGRAM
VCC
REF
GND
CT
COMP
UVLO
& BIAS
3.0V
REFERENCE
SET
RESET
CROWBAR
2-PHASE
DRIVER
LOGIC
CMP3
DAC+24%
OSCILLATOR
ADP3162
CMP
CMP2
DAC–18%
CMP
CMP1
VID
DAC
gm
PWM1
PWM2
PWRGD
CS–
CS+
FB
GENERAL DESCRIPTION
The ADP3162 is a highly efficient dual output synchronous
buck switching regulator controller optimized for converting a
5 V or 12 V main supply into the core supply voltage required by
high-performance processors such as Tualatin. The ADP3162
uses an internal 5-bit DAC to read a voltage identification (VID)
code directly from the processor, which is used to set the output
voltage between 1.05 V and 1.825 V. The ADP3162 uses a
current mode PWM architecture to drive two logic-level outputs
at a programmable switching frequency that can be optimized
for VRM size and efficiency. The output signals are 180 degrees
out of phase, allowing for the construction of two complementary
buck switching stages. These two stages share the dc output
current to reduce overall output voltage ripple. An active cur-
rent balancing function ensures that both phases carry equal
portions of the total load current, even under large transient
loads, to minimize the size of the inductors.
VID3 VID2 VID1 VID0 VID25
The ADP3162 also uses a unique supplemental regulation tech-
nique called active voltage positioning to enhance load transient
performance. Active voltage positioning results in a dc/dc converter
that meets the stringent output voltage specifications for high
performance processors, with the minimum number of output
capacitors and smallest footprint. Unlike voltage-mode and
standard current-mode architectures, active voltage positioning
adjusts the output voltage as a function of the load current so
that it is always optimally positioned for a system transient. The
ADP3162 also provides accurate and reliable short circuit pro-
tection and adjustable current limiting.
The ADP3162 is specified over the commercial temperature
range of 0°C to 70°C and is available in a 16-lead narrow body
SOIC package.
ADOPT is a trademark of Analog Devices, Inc.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
1 page  
ADP3162
5-BIT CODE
1k
4.7nF
ADP3162
1 VID3
2 VID2
3 VID1
4 VID0
5 VID25
6 COMP
7 FB
8 CT
VCC 16
REF 15
CS– 14
PWM1 13
PWM2 12
CS+ 11
PWRGD 10
GND 9
AD820
1.2V
+
1F
12V
100nF
VFB
Figure 1. Closed-Loop Output Voltage Accuracy Test Circuit
Table I. Output Voltage vs. VID Code
VID25
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
VID3
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
VID2
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
VID1
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
VID0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
VOUT(NOM)
1.050 V
1.075 V
1.100 V
1.125 V
1.150 V
1.175 V
1.200 V
1.225 V
1.250 V
1.275 V
1.300 V
1.325 V
1.350 V
1.375 V
1.400 V
1.425 V
1.450 V
1.475 V
1.500 V
1.525 V
1.550 V
1.575 V
1.600 V
1.625 V
1.650 V
1.675 V
1.700 V
1.725 V
1.750 V
1.775 V
1.800 V
1.825 V
THEORY OF OPERATION
The ADP3162 combines a current-mode, fixed frequency PWM
controller with antiphase logic outputs in a controller for a two-
phase synchronous buck power converter. Two-phase operation
is important for switching the high currents required by high
performance microprocessors. Handling the high current in a
single-phase converter would place difficult requirements on the
power components such as inductor wire size, MOSFET ON-
resistance and thermal dissipation. The ADP3162’s high side
current sensing topology ensures that the load currents are bal-
anced in each phase, such that neither phase has to carry more
than half of the power. An additional benefit of high side current
sensing over output current sensing is that the average current
through the sense resistor is reduced by the duty cycle of the
converter allowing the use of a lower power, lower cost resistor.
The outputs of the ADP3162 are logic drivers only and are
not intended to directly drive external power MOSFETs.
Instead, the ADP3162 should be paired with drivers such as
the ADP3412, ADP3413, or ADP3414.
The frequency of the ADP3162 is set by an external capacitor
connected to the CT pin. Each output phase of the ADP3162
operates at half of the frequency set by the CT pin. The error
amplifier and current sense comparator control the duty cycle of
the PWM outputs to maintain regulation. The maximum duty
cycle per phase is inherently limited to 50% because the PWM
outputs toggle in two-phase operation. While one phase is on,
the other phase is off. In no case can both outputs be high at the
same time.
Output Voltage Sensing
The output voltage is sensed at the FB pin allowing for remote
sensing. To maintain the accuracy of the remote sensing, the
GND pin should also be connected close to the load. A voltage
error amplifier (gm) amplifies the difference between the output
voltage and a programmable reference voltage. The reference
voltage is programmed between 1.05 V and 1.825 V by an internal
5-bit DAC, which reads the code at the voltage identification
(VID) pins. (Refer to Table I for the output voltage versus VID pin
code information.)
Active Voltage Positioning
The ADP3162 uses Analog Devices Optimal Positioning Tech-
nology (ADOPT), a unique supplemental regulation technique
that uses active voltage positioning and provides optimal com-
pensation for load transients. When implemented, ADOPT adjusts
the output voltage as a function of the load current, so that it is
always optimally positioned for a load transient. Standard (passive)
voltage positioning has poor dynamic performance, rendering
it ineffective under the stringent repetitive transient conditions
required by high performance processors. ADOPT, however,
provides optimal bandwidth for transient response that yields
optimal load transient response with the minimum number of
output capacitors.
Reference Output
A 3.0 V reference is available on the ADP3162. This reference
is normally used to set the voltage positioning accurately using a
resistor divider to the COMP pin. In addition, the reference can
be used for other functions such as generating a regulated voltage
with an external amplifier. The reference is bypassed with a 1 nF
capacitor to ground. It is not intended to supply current to large
capacitive loads, and it should not be used to provide more than
1 mA of output current.
REV. A
–5–
5 Page 
ADP3162
LAYOUT AND COMPONENT PLACEMENT GUIDELINES
The following guidelines are recommended for optimal perfor-
mance of a switching regulator in a PC system.
General Recommendations
1. For good results, at least a four-layer PCB is recommended.
This should allow the needed versatility for control circuitry
interconnections with optimal placement, a signal ground
plane, power planes for both power ground and the input
power (e.g., 5 V), and wide interconnection traces in the
rest of the power delivery current paths. Keep in mind that
each square unit of 1 ounce copper trace has a resistance
of ~ 0.53 mΩ at room temperature.
2. Whenever high currents must be routed between PCB
layers, vias should be used liberally to create several parallel
current paths so that the resistance and inductance intro-
duced by these current paths is minimized and the via
current rating is not exceeded.
3. If critical signal lines (including the voltage and current
sense lines of the ADP3162) must cross through power
circuitry, it is best if a signal ground plane can be inter-
posed between those signal lines and the traces of the
power circuitry. This serves as a shield to minimize noise
injection into the signals at the expense of making signal
ground a bit noisier.
4. The power ground plane should not extend under signal
components, including the ADP3162 itself. If necessary,
follow the preceding guideline to use the signal ground
plane as a shield between the power ground plane and the
signal circuitry.
5. The GND pin of the ADP3162 should be connected first
to the timing capacitor (on the CT pin), and then into the
signal ground plane. In cases where no signal ground plane
can be used, short interconnections to other signal ground
circuitry in the power converter should be used.
6. The output capacitors of the power converter should be
connected to the signal ground plane even though power
current flows in the ground of these capacitors. For this
reason, it is advised to avoid critical ground connections
(e.g., the signal circuitry of the power converter) in the
signal ground plane between the input and output capaci-
tors. It is also advised to keep the planar interconnection
path short (i.e., have input and output capacitors close
together).
7. The output capacitors should also be connected as closely
as possible to the load (or connector) that receives the power
(e.g., a microprocessor core). If the load is distributed, the
capacitors also should be distributed, and generally in pro-
portion to where the load tends to be more dynamic.
8. Absolutely avoid crossing any signal lines over the switching
power path loop, described below.
Power Circuitry
9. The switching power path should be routed on the PCB to
encompass the smallest possible area in order to minimize
radiated switching noise energy (i.e., EMI). Failure to take
proper precaution often results in EMI problems for the entire
PC system as well as noise-related operational problems in
the power converter control circuitry. The switching power
path is the loop formed by the current path through the
input capacitors, the power MOSFETs, and the power
Schottky diode, if used (see next), including all intercon-
necting PCB traces and planes. The use of short and wide
interconnection traces is especially critical in this path for two
reasons: it minimizes the inductance in the switching loop,
which can cause high-energy ringing, and it accommodates
the high current demand with minimal voltage loss.
10. An optional power Schottky diode (3 A–5 A dc rating) from
each lower MOSFET’s source (anode) to drain (cathode)
will help to minimize switching power dissipation in the
upper MOSFETs. In the absence of an effective Schottky
diode, this dissipation occurs through the following sequence
of switching events. The lower MOSFET turns off in advance
of the upper MOSFET turning on (necessary to prevent
cross-conduction). The circulating current in the power
converter, no longer finding a path for current through the
channel of the lower MOSFET, draws current through the
inherent body diode of the MOSFET. The upper MOSFET
turns on, and the reverse recovery characteristic of the
lower MOSFET’s body diode prevents the drain voltage
from being pulled high quickly. The upper MOSFET then
conducts very large current while it momentarily has a high
voltage forced across it, which translates into added power
dissipation in the upper MOSFET. The Schottky diode
minimizes this problem by carrying a majority of the circu-
lating current when the lower MOSFET is turned off, and
by virtue of its essentially nonexistent reverse recovery time.
The Schottky diode has to be connected with very short
copper traces to the MOSFET to be effective.
11. A small ferrite bead inductor placed in series with the drain
of the lower MOSFET can also help to reduce this previ-
ously described source of switching power loss.
12. Whenever a power dissipating component (e.g., a power
MOSFET) is soldered to a PCB, the liberal use of vias,
both directly on the mounting pad and immediately sur-
rounding it, is recommended. Two important reasons for
this are: improved current rating through the vias, and
improved thermal performance from vias extended to the
opposite side of the PCB where a plane can more readily
transfer the heat to the air.
13. The output power path, though not as critical as the switch-
ing power path, should also be routed to encompass a small
area. The output power path is formed by the current path
through the inductor, the current sensing resistor, the out-
put capacitors, and back to the input capacitors.
14. For best EMI containment, the power ground plane should
extend fully under all the power components except the
output capacitors. These components are: the input capaci-
tors, the power MOSFETs and Schottky diodes, the
inductors, the current sense resistor, and any snubbing
element that might be added to dampen ringing. Avoid
extending the power ground under any other circuitry or
signal lines, including the voltage and current sense lines.
REV. A
–11–
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet ADP3162.PDF ] | |
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