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PDF ADP3153 Data sheet ( Hoja de datos )
| Número de pieza | ADP3153 | |
| Descripción | 5-Bit Programmable Dual Power Supply Controller for Pentium II Processor | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ADP3153 (archivo pdf) en la parte inferior de esta página. Total 12 Páginas | ||
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FEATURES
5-Bit Digitally Programmable 1.8 V to 3.5 V Output
Voltage
Dual N-Channel Synchronous Driver
Total Output Accuracy ؎1% (0؇C to +70؇C)
High Efficiency
Current-Mode Operation
Short Circuit Protection
Power Good Output
Overvoltage Protection Crowbar
On-Board Linear Regulator Controller
VRM 8.2 Compatible
Narrow Body TSSOP 20-Lead Package
APPLICATIONS
Desktop PC Power Supply for:
Pentium II Processor
Deschutes Processor
Pentium Pro Processor
Pentium Processor
AMD–K6 Processor
VRM Modules
5-Bit Programmable Dual
Power Supply Controller
for Pentium® II Processor
ADP3153
GENERAL DESCRIPTION
The ADP3153 is a highly efficient synchronous switching regu-
lator controller and a linear regulator controller. The switching
regulator controller is optimized for Pentium II and Deschutes
Processor applications where 5 V is stepped down to a digitally
controlled output voltage between 1.8 V and 3.5 V. Using a 5-bit
DAC to read a voltage identification (VID) code directly from
the processor, the ADP3153 uses a current mode constant off-
time architecture to generate its precise output voltage.
The ADP3153 drives two N-channel MOSFETS in a synchro-
nous rectified buck converter, at a maximum switching fre-
quency of 250 kHz. Using the recommended loop compensation
and guidelines, the ADP3153 provides a dc/dc converter that
meets Intel’s stringent transient specifications with a minimum
number of output capacitors and smallest footprint. Addition-
ally, the current mode architecture also provides guaranteed
short circuit protection and adjustable current limiting.
The ADP3153’s linear regulator controller drives an external
N-channel device. The output voltage is set by the ratio of the
external feedback resistors. The controller has been designed for
excellent load transient response.
VCC
+12V
VIN
+5V
VO2
+3.3V
1A
R1
VIN
+5V R2
IRL2703
1000F
35k⍀
20k⍀
22F 1F
CCOMP
SD VCC
DRIVE1
CMP
ADP3153
VLDO
SENSE+
SENSE–
IRL3103
1nF
150pF
FB DRIVE2
CT PGND
AGND
VID0–VID4
IRL3103
+ CIN
L
2.5H
RSENSE
7m⍀
10BQ015
+ CO
VO
1.8V–3.5V
14A
5-BIT CODE
Figure 1. Typical Application
Pentium is a registered trademark of Intel Corporation.
All other trademarks are the property of their respective holders.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1998
1 page  
100
SEE FIGURE 2
95
VOUT = +3.5V
90
85
VOUT = +2.0V
80
VOUT = +2.8V
75
70
65
1.4 2.8 4.2 5.6 7.0 8.4 9.8 11.2 12.6 14.0
OUTPUT CURRENT – Amps
Figure 4. Efficiency vs. Output Current
Typical Performance Characteristics–ADP3153
450
400
350
300
250
200
150
100
50
0
50 100 200 300 400 500 600 700 800
TIMING CAPACITOR – pF
Figure 5. Frequency vs. Timing
Capacitor
45
40
35
30
25
20
15
10
5
0
45
Qn + Qn = 100nC
58 83 134
OPERATING FREQUENCY – kHz
397
Figure 6. Gate Charge vs. Supply
Current
SEE FIGURE 2
VOUT = +3.5V, IOUT = 10A
PRIMARY
N-DRIVE
DRIVER OUTPUT
1
SECONDARY
N-DRIVE
DRIVER OUTPUT
2
DRIVE 1 AND 2 = 5V/DIV
500ns/DIV
Figure 7. Gate Switching Waveforms
SEE FIGURE 2
VCC = +12V
VIN = +5V
VOUT = +3.5V
IOUT = 10A
100ns/DIV
Figure 8. Driver Transition Waveforms
OUTPUT VOLTAGE
20mV/DIV
OUTPUT CURRENT
14A TO 1A
10s/DIV
Figure 9. Transient Response,
14 A–1A of Figure 2 Circuit
OUTPUT VOLTAGE
20mV/DIV
OUTPUT CURRENT
1A TO 14A
10s/DIV
Figure 10. Transient Response,
1A–14 A of Figure 2 Circuit
VCC VOLTAGE
5V/DIV
3
REGULATOR
OUTPUT VOLTAGE
1V/DIV
4
10ms/DIV
Figure 11. Power-On Start-Up
Waveforms
25
TA = +25؇C
SEE FIGURE 13
20
15
10
5
0
OUTPUT ACCURACY – %
Figure 12. Output Accuracy Distribution
REV. 0
–5–
5 Page 
ADP3153
BOARD LAYOUT
A multilayer PCB is recommended with a minimum of two
copper layers. One layer on top should be used for traces inter-
connecting low power SMT components. The ground terminals
of those components should be connected with vias to the bot-
tom traces connecting directly to the ADP3153 ground pins.
One layer should be a power ground plane. If four layers are
possible, one additional layer should be an internal system
ground plane, and one additional layer can be used for other
system interconnections.
When laying out the printed circuit board, the following check-
list should be used to ensure proper operation of the ADP3153.
Board Layout Guidelines
1. The power loop should be routed on the PCB to encompass
small areas to minimize radiated switching noise energy to
the control circuit and thus to avoid circuit problems caused
by noise. This technique also helps to reduce radiated EMI.
The power loop includes the input capacitors, the two
MOSFETs, the sense resistor, the inductor and the output
capacitors. The ground terminals of the input capacitors,
the low side FET, the ADP3153 and the output capacitors
should be connected together with short and wide traces. It is
best to use an internal ground plane.
2. The PGND (power ground) pin of the ADP3153 must re-
turn to the grounded terminals of the input and output ca-
pacitors and to the source of the low side MOSFET with the
shortest and widest traces possible. The AGND (analog
ground) pin has to be connected to the ground terminals of
the timing capacitor and the compensating capacitor, again
with the shortest leads possible, and before it is connected to
the PGND pin.
3. The positive terminal of the input capacitors must be con-
nected to the drain of the high side MOSFET. The source
terminal of this FET is connected to the drain of the low side
FET, (whose source is connected to the ground plane direct)
with the widest and shortest traces possible. To kill parasitic
ringing at the input of the buck inductor due to parasitic
capacitances and inductances, a small (L > 3 mm) ferrite
bead is recommended to be placed in the drain lead of the
low side FET. Also, to minimize dissipation of the high side
FET, a low voltage 1 A Schottky diode can be connected
between the input of the buck inductor and the source of the
low side FET.
4. The positive terminal of the bypass capacitors of the +12 V
supply must be connected to the VIN pin of the ADP3153
with the shortest leads possible. The negative terminals must
be connected to the PGND pin of the ADP3153.
5. The sense pins of the ADP3153 must be connected to the
sense resistor with as short traces as possible. Make sure that
the two sense traces are routed together with minimum sepa-
ration (<1 mm). The output side of the sense resistor should
be connected to the VCC pin(s) of the CPU with as short and
wide PCB traces as possible to reduce the VCC voltage drop.
(Each square unit of 1 ounce Cu-trace has a resistance of
~0.53 mΩ. At 14 A, each mΩ of PCB trace resistance be-
tween current sense resistor output and VCC terminal(s) of
the CPU will reduce the regulated output voltage by 14 mV.
The filter capacitors to ground at the sense terminals of the
IC should be as close as possible (<8 mm) to the ADP3153.
The common ground of the optional filter capacitors should
be connected to the AGND pin of the ADP3153 with the
shortest traces possible (<10 mm).
6. The microprocessor load should be connected to the output
terminals of the converter with the widest and shortest traces
possible. Use overlapping traces in different layers to mini-
mize interconnection inductance.
REV. 0
–11–
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet ADP3153.PDF ] | |
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