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PDF ADP3088 Data sheet ( Hoja de datos )
| Número de pieza | ADP3088 | |
| Descripción | 1 MHz/ 750 mA Buck Regulator | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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PRELIMINARY TECHNICAL DATA
a
1MHz,750mABuckRegulator
Preliminary Technical Data
FEATURES
1 MHz PWM Frequency
Automatic PWM to Power Saving Mode at Light Load
Fully Integrated 1 A Power Switch
3% Output Regulation Accuracy over Temperature,
Line, and Load
100% Duty Cycle Operation
Simple Compensation
Output Voltage: 1.25 V to 10.5 V
Small Inductor and MLC Capacitors
Low Quiescent Current while Pulse Skipping
Thermal Shutdown
Fully Integrated Soft Start
Cycle-by-cycle Current Limit
APPLICATONS
PDAs and Palmtop Computers
Notebook Computers
PCMCIA Cards
Bus Products
Portable Instruments
IN
IN
COMP
GND
GND
ADP3088
FUNCTIONAL BLOCK DIAGRAM
CURRENT
SENSE
AMP
PWM
1MHz
COMPARATOR
SQ
R
SW
DRV
PROTECTION
LOGIC
(ILIM, OT)
RUN/STOP
COMPARATORS
ERROR
AMP
gm
+ REF
1.245V
SOFT-START
TIMER
FB
GENERAL DESCRIPTION
The ADP3088 is a high frequency, non-synchronous PWM
step-down DC-DC regulator with an integrated 1A power
switch in a space-saving MSOP8 package. It provides high
efficiency, excellent dynamic response, and is very simple
to use.
The ADP3088’s 1 MHz switching frequency allows for
small, inexpensive external components, and the current
mode control loop is simple to compensate and eases noise
filtering. It operates in PWM current mode under heavy
loads and saves energy at lighter loads by switching auto-
matically into Power Saving mode. Soft start is integrated
completely on chip, as is the cycle-by-cycle current limit.
Capable of operating from 2.5 V to 11 V input, it is ideal for
many applications, including portable, battery power appli-
cations, where local point-of-use power regulation is re-
quired. Supporting output voltages down to 1.25 V, the
ADP3088 is ideal to generate low voltage rails, providing
the optimal solution in its class for delivering power effi-
ciently, responsively, and simply with minimal printed cir-
cuit board area.
The device is specified over the industrial temperature
range of -40 °C to +85°C.
VIN
3.3V
10µF
0.1µF
4.7pF
ADP3088
IN SW
IN DRV
GND GND
COMP FB
220pF
20kΩ
3.3µH
10.0kΩ
1N5817
22.4kΩ
Figure 1. Typical Application
VOUT
1.8V
10µF
REV. PrK
3/28/02
Information furnished by Analog Devices is believed to be accurate and reli-
able. However, no responsibility is assumed byAnalog Devices for its use, nor
for any infringements of patents or other rights of third parties which may
result from its use. No license is granted by implication or otherwise under any
patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 2002
1 page  
PRELIMINARY TECHNICAL DATA
ground. For some VIN and ILOAD configurations, the DRV
pin must be grounded for reliable operation.
APPLICATION INFORMATION
Output Voltage Setting
In its standard usage, the output voltage of the ADP3088 is
programmed to a desired fixed value by a resistor divider
from the output voltage into the feedback node, the pin FB,
at which node the control loop ensures regulation at the
reference level, VREF. The divider should be designed to
satisfy the formula:
VOUT
= VREF
× 1+
RB
RA
(1)
where RA is the upper divider resistor (between the output
and FB) and RB is the lower one (between FB and ground).
RA and RB are recommended to have values in the range of
2~200 kΩ and are likely to require a 1% tolerance or better
to attain acceptable output voltage tolerance.
In less conventional applications described separately, the
resistor feedback configuration can be modified or tapped
with other resistors to affect current flow into the FB node
that, in turn, influences the output voltage. Even a switched
voltage can be summed into the FB node as long as it is
sufficiently integrated and does not intolerably compromise
the transient response. This latter application is considered
further below in an application for powering a DSP.
Input Voltage, Power Dissipation Considerations, and
Power Savings Mode
The input voltage range is not typically considered a critical
parameter for electrical functionality, but there are several
considerations, upon which there is further elaboration
below:
1. VIN must never exceed the maximum rated voltage
2. VIN must be within the specified operating range when
normal operation is expected
3. VIN must be greater than VOUT by at least the specified
headroom when DC regulation is expected
4. VIN, if not sufficiently greater than VOUT, may limit the
large signal transient response of a buck converter
5. VIN, if much greater than VOUT, may give rise to such a
low duty ratio that it activates power savings mode even
at static higher load conditions or upon dynamic load
changes when it is not desired.
6. VIN affects the device power dissipation (a lower value
causes higher dissipation), which in turn affects die
temperature that must be kept below a maximum rat-
ing.
The lowest input voltage together with the maximum out-
put voltage and maximum current create the conditions for
maximum power dissipation in the device, which determine
maximum temperature rise that should be checked against
the maximum junction temperature rating. The formula for
maximum power dissipation in the device is given by:
ADP3088
PDMAX
=
VO
+VF@IO,MAX
VIN
×IO,MAX
×VSW@IO,MAX
(2)
where VF is the diode forward voltage drop and VSW is the
drop across the internal switch and current sensing resistor
that appears between the VIN and SW pins of the
ADP3088 during the on state of the switch. Both of these
variables can be approximated from a combination of
worst-case specs and typical graphs. Multiply the power
dissipation by the thermal resistance from junction to case
or ambient, as desired, to determine internal temperature
rise.
If the input voltage were so much higher than the output
voltage that it required an average duty ratio less than an
internally preset threshold, then power savings mode
(“PSM”) – that is characterized by periodic shutdown and
wakeup of the device that reduces average quiescent cur-
rent – would be active for all load conditions rather than
only at lighter loads, for which it is intended. PSM opera-
tion is characterized by low-frequency ripple on the output
that appears similar to the behavior of a hysteretic regula-
tor. This is usually not a factor for consideration and may
be ignored if PSM operation is acceptable for all load con-
ditions, but in case it is relevant, the following recommen-
dation is offered:
VIN
<
VO + VF
DPSM(MAX)
(3)
It is not possible to prevent the duty ratio from tending
towards zero in non-synchronous buck converters below a
certain minimum load current level called "borderline cur-
rent" or "critical current" for the power converter. That
corresponds to the inductor ripple current reaching zero at
its bottom peak - sometimes called the "valley current". If
PSM activation strains the lower regulation limit due to the
hysteretic ripple, the output voltage can be offset slightly
upward by readjusting the nominal voltage setpoint with the
resistor divider.
Even though a buck converter may have a low dropout
voltage that allows the static regulation to be maintained as
the input voltage drops near to the output voltage, in buck
converters the slew rate limitation of inductor current can
compromise the dynamic regulation in response to load
current step increases. That is because the maximum rate
that current can be increased in the inductor is proportional
to the voltage available to impress across it, which is com-
promised as the input voltage reduces toward the output
voltage. This is not a limitation of the device but of buck
converters in general. The limitation is considered as part
of the output filter design, although it could also be consid-
ered in terms of a minimum acceptable input voltage for a
given output filter that will ensure that the dynamic re-
sponse is acceptably maintained.
Output Filter Components
In most applications it is desirable to use the smallest induc-
tor value that does not introduce practical problems, as this
tends to yield the lowest cost inductor. One reason for using
an even larger inductor than the minimum tolerable might
be to reduce output ripple voltage further, but cost being
REV. PrK
–5–
5 Page 
PRELIMINARY TECHNICAL DATA
RM-8
8-Lead Mini/micro SOIC Package [Mini_SO]
0.122 (3.10)
0.114 (2.90)
0.122 (3.10)
0.114 (2.90)
8
1
5
0.199 (5.05)
0.187 (4.75)
4
PIN 1
0.0256 (0.65) BSC
0.120 (3.05)
0.120 (3.05)
0.112 (2.84)
0.112 (2.84)
0.006 (0.15)
0.002 (0.05)
SEATING
PLANE
0.043 (1.09)
0.037 (0.94)
33؇
0.018 (0.46)
0.008 (0.20)
0.011 (0.28) 27؇
0.003 (0.08)
0.028 (0.71)
0.016 (0.41)
ADP3088
REV. PrK
–11–
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet ADP3088.PDF ] | |
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