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PDF ADP3020 Data sheet ( Hoja de datos )
| Número de pieza | ADP3020 | |
| Descripción | High-Efficiency Notebook Computer Power Supply Controller | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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a
High-Efficiency Notebook Computer
Power Supply Controller
ADP3020
FEATURES
Wide Input Voltage Range: 4.5 V to 25 V
High Conversion Efficiency > 96%
Integrated Current Sense—No External Resistor Required
Low Shutdown Current: 7 A (Typical)
Dual Synchronous Buck Controllers with Selectable
PWM/Power-Saving Mode Operation
Built-In Gate Drive Boost Circuit for Driving External
N-Channel MOSFETs
Two Independently Programmable Output Voltages
Fixed 3.3 V or Adjustable (1.25 V to VIN–0.5 V)
Fixed 5 V or Adjustable (1.25 V to VIN–0.5 V)
Programmable PWM Frequency
Integrated Linear Regulator Controller
Extensive Circuit Protection Functions
38-Lead TSSOP Package
APPLICATIONS
Notebook Computers and PDAs
Portable Instruments
General Purpose DC-DC Converters
GENERAL DESCRIPTION
The ADP3020 is a highly efficient dual synchronous buck switch-
ing regulator controller optimized for converting the battery or
adapter input into the system supply voltages required in note-
book computers. The ADP3020 uses a dual-mode PWM/Power
Saving Mode architecture to maintain efficiency over a wide
load range. The oscillator frequency can be programmed for
200 kHz, 300 kHz, or 400 kHz operation, or it can be synchro-
nized to an external clock signal of up to 600 kHz.
The ADP3020 provides accurate and reliable short circuit pro-
tection using an internal current sense circuit, which reduces
cost and increases overall efficiency. Other protection features
include programmable soft-start, UVLO, and integrated output
undervoltage/overvoltage protection. The ADP3020 contains a
linear regulator controller that is designed to drive an external
P-channel MOSFET or PNP transistor. The linear regulator
output is adjustable, and can be used to generate the auxiliary
voltages required in many laptop designs.
VIN
5.5V TO 25V
5V
FUNCTIONAL BLOCK DIAGRAM
Q3
L2
Q4
ADP3020
5V LINEAR 1.20V
REF
PFO
5V
SMPS
3.3V
SMPS
Q1
L1
Q2
3.3V
SS5
PWRGD
POWER-ON
RESET
LINEAR
CONTROLLER
SS3
Q5
2.5V
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
1 page  
ADP3020
Pin No.
31
32
Mnemonic
INTVCC
AUXVCC
33 SD
34 PGND
35 DRVL5
36 SW5
37 DRVH5
38 BST5
PIN FUNCTION DESCRIPTIONS (Continued)
Function
Linear Regulator Bypass for the internal 5 V LDO. Bypass this pin with a 4.7 µF capacitor to AGND.
Supply Switch Over. When AUXVCC > 4.75 V, and both of the switchers are in Power Saving mode,
the internal 5 V LDO is turned off. The chip is powered by AUXVCC pin. There is a 2% hysteresis for
this pin.
Shutdown Control Input, Active Low. If SD = 0 V, the chip is in shutdown with very low quiescent cur-
rent. For automatic start-up, connect SD to VIN directly.
Power Ground.
Low Side Driver for 5 V Buck Converter.
Switching Node (Inductor) Connection for 5 V Buck Converter.
High Side Gate Driver for 5 V Buck Converter.
Boost Capacitor Connection for High Side Gate Driver of the 5 V Buck Converter.
ABSOLUTE MAXIMUM RATINGS*
VIN to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +27 V
AGND to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 0.3 V
INTVCC . . . . . . . . . . . . . . . . . . . . . . AGND – 0.3 V to +6 V
BST5, BST3 to PGND . . . . . . . . . . . . . . . . . –0.3 V to +32 V
BST5 to SW5 . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
BST3 to SW3 . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
CS5, CS3 . . . . . . . . . . . . . . . . . . . . . . AGND – 0.3 V to VIN
SW3, SW5 to PGND . . . . . . . . . . . . . . –0.3 V to VIN + 0.3 V
SD . . . . . . . . . . . . . . . . . . . . . . . . . AGND – 0.3 V to +27 V
DRVL5/3 to PGND . . . . . . . . . –0.3 V to (INTVCC + 0.3 V)
DRVH5/3 to SW5/3 . . . . . . . . . –0.3 V to (INTVCC + 0.3 V)
All Other Inputs and Outputs
. . . . . . . . . . . . . . . . . . AGND – 0.3 V to INTVCC + 0.3 V
θJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98°C/W
Operating Ambient Temperature Range . . . . –40°C to +85°C
Junction Temperature Range . . . . . . . . . . . . –40°C to +150°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . . 300°C
*This is a stress rating only; operation beyond these limits can cause the device to
be permanently damaged.
PIN CONFIGURATION
CS5 1
38 BST5
FB5 2
37 DRVH5
EAN5 3
36 SW5
EAO5 4
35 DRVL5
ADJ/FX5 5
SS5 6
34 PGND
33 SD
CLSET5 7 ADP3020 32 AUXVCC
REF 8
31 INTVCC
TOP VIEW
AGND 9 (Not to Scale) 30 VIN
CLSET3 10
29 DRVL3
MODE 11
28 SW3
SYNC 12
27 DRVH3
SS3 13
26 BST3
ADJ/FX3 14
EAO3 15
25 DRV2
24 FB2
EAN3 16
23 SD2
FB3 17
22 CPOR
CS3 18
PFI 19
21 PWRGD
20 PFO
Model
ADP3020ARU
ORDERING GUIDE
Temperature Range
–40°C to +85°C
Package Description
Thin Shrink Small Outline
Package Option
RU-38
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADP3020 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–5–
5 Page 
ADP3020
Synchronous Rectifier (DRVL)
Synchronous rectification is used to reduce conduction losses
and to ensure proper start-up of the boost gate driver circuit.
Antishoot-through protection has been included to prevent cross
conduction during switch transitions. The low side driver must
be turned off before the high side driver is turned on. For typi-
cal N-channel MOSFETs, the dead time is about 50 ns. On the
other edge, a dead time of about 50 ns is achieved by an internal
delay circuit. The synchronous rectifier is turned off when the
current flowing through the low-side MOSFET falls to zero when
in Discontinuous Conduction (DCM) PWM mode and PSV mode.
In Continuous Conduction (CCM) PWM mode, the current
flowing through the low-side MOSFET never reaches zero, so the
synchronous rectifier is turned off by the next clock cycle.
Oscillator Frequency and Synchronization (SYNC)
The SYNC pin controls the oscillator frequency. When SYNC
= 0 V, fOSC = 200 kHz ; when SYNC = REF, fOSC = 300 kHz;
when SYNC = 5 V, fOSC = 400 kHz. 400 kHz operation will
minimize external component size and cost while 200 kHz opera-
tion provides better efficiency and lower dropout. The SYNC
pin can also be used to synchronize the oscillator with an exter-
nal 5 V clock signal. A low-to-high transition on SYNC initiates
a new cycle. Synchronization range is 230 kHz to 600 kHz.
Shutdown (SD)
Holding SD = GND low will put the ADP3020 into ultralow
current shutdown mode. For automatic start-up, SD can be tied
directly to VIN.
Soft-Start and Power-Up Sequencing (SS)
SS3 and SS5 are soft start pins for the two controllers. A 4 µA
pull-up current is used to charge an external soft start capacitor.
Power-up sequencing can be easily done by choosing different
size external capacitors. When SS3/SS5 < 1.2 V, the two switch-
ing regulators are turned off. When 1.2 V < SS5/SS3 < 2.6 V,
the regulators start working in soft start mode. When SS3/SS5 >
2.6 V, the regulators are in normal operating mode. The con-
trollers are forced to stay in PWM mode during the soft-start
period. The minimum soft-start time (~20 µs) is set by an inter-
nal capacitor. Table II shows the ADP3020 operating modes.
Current Limiting (CLSET)
A cycle-by-cycle current limiting scheme is used by monitoring
current through the top N-channel MOSFET when it is turned
on. By measuring the voltage drop across the high-side MOSFET
VDS(ON), the external sense resistor can be deleted. The current
limit value can be set by CLSET. When CLSET = Floating, the
maximum VDS(ON) = 72 mV at room temperature; when CLSET
= 0 V, the maximum VDS(ON) = 144 mV at room temperature. An
external resistor can be connected between CLSET and AGND
to choose a value between 72 mV and 144 mV. The temperature
coefficient of RDS(ON) of the N-channel MOSFET is canceled by
the internal current limit circuitry, so that an accurate current
limit value can be obtained over a wide temperature range. In
PSV mode, the current limit value is reduced to about 1/4 of
the value in PWM mode to reduce the interference noise to other
components on the PC board.
Output Undervoltage Protection
Each switching controller has an undervoltage protection circuit.
When the current flowing through the high-side MOSFET
reaches the current limit continuously for eight clock cycles,
and the output voltage is below 20% of the nominal output
voltage, both controllers will be latched off and will not restart
until SD or SS3/SS5 is toggled, or until VIN is cycled below 4 V.
This feature is disabled during soft start.
Output Overvoltage Protection
Both converter outputs are continuously monitored for overvolt-
age. If either output voltage is higher than the nominal output
voltage by more than 20%, both converter’s high-side gate drivers
(DRVH5/3) will be latched off, and the low-side gate drivers
will be latched on, and will not restart until SD or SS5/SS3 are
toggled, or until VIN is cycled below 4 V. The low-side gate
driver (DRVL) is kept high when the controller is in off-state
and the output voltage is less than 93% of the nominal output
voltage. Discharging the output capacitors through the main
inductor and low-side N-channel MOSFET will cause the out-
put to ring. This will make the output momentarily go below
GND. To prevent damage to the circuit, use a reverse-biased
1 A Schottky diode across the output capacitors to clamp the
negative surge.
Power Good Output (PWRGD)
The ADP3020 also provides a PWRGD signal for the micropro-
cessor. During start-up, the PWRGD pin is held low until 5 V
output is within –4% of its preset voltage. Then, after a time
delay determined by an external timing capacitor connected from
CPOR to GND, PWRGD will be actively pulled up to INTVCC
by an external pull-up resistor. CPOR can also be used as a
manual reset (MR) function. When the 5 V output is lower than
the preset voltage by more than 8%, PWRGD is immediately
pulled low.
Linear Regulator Controller
The ADP3020 includes an onboard linear regulator controller.
An external PNP transistor can be used for operation up to 1 A.
For higher output current applications, a low threshold PMOS
can be used as the pass transistor. The output voltage can be set
by a resistor divider. The minimum output voltage of the LDO
is 1.25 V, while the maximum output voltage depends on where
the LDO input is connected and the dropout voltage of the
external pass transistor.
SD
Low
High
High
High
High
High
Table II. Operating Modes
SS5
X
SS5 < 1.2 V
1.2 V < SS5 < 2.6 V
2.6 V < SS5
X
X
SS3
X
SS3 < 1.2 V
X
X
1.2 V < SS3 < 2.6 V
2.6 V < SS3
Mode
Shutdown
Standby
Run
Run
Run
Run
Description
All Circuits Turned Off
5 V and 3.3 V Off; INTVCC = 5 V, REF = 1.2 V
5 V in Soft Start
5 V in Normal Operation
3.3 V in Soft Start
3.3 V in Normal Operation
REV. 0
–11–
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet ADP3020.PDF ] | |
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