PDF ADN8810 Data sheet ( Hoja de datos )

Número de pieza	ADN8810
Descripción	12-Bit High Output Current Source
Fabricantes	Analog Devices
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No Preview Available ! 12-Bit High Output Current Source ADN8810 FEATURES High precision 12-bit current source Low noise Long term stability Current output from 0 mA to 300 mA Output fault indication Low drift Programmable maximum current 24-lead 4 mm × 4 mm leadframe chip scale package 3-wire serial interface APPLICATIONS Tunable laser current source Programmable high output current source Automatic test equipment GENERAL DESCRIPTION The ADN8810 is a 12-bit current source with an adjustable full-scale output current of up to 300 mA. The full-scale out- put current is set with two external sense resistors. The output compliance voltage is 2.5 V, even at output currents up to 300 mA. The device is particularly suited for tunable laser control and can drive tunable laser front mirror, back mirror, phase, gain, and amplification sections. A host CPU or microcontroller controls the operation of the ADN8810 over a 3-wire SPI® interface. The 3-bit address allows up to eight devices to be independently controlled while attached to the same SPI bus. The ADN8810 is guaranteed with ± 4 LSB INL and ± 0.75 LSB DNL. Noise and digital feedthrough are kept low to ensure low jitter operation for laser diode applications. Full-scale and scaled output currents are given in Equations 1 and 2, respectively. IFS ≈ VREF 10 × RSN (1) IOUT = Code × VREF 4096 × 1 RSN × ⎜⎛ ⎜⎝ RSN 15k + 0.1⎟⎟⎠⎞ (2) FUNCTIONAL BLOCK DIAGRAM 5V 5V 3.3V RESET 4.096V SERIAL INTERFACE ADDRESS ENCOMP DVDD AVDD PVDD RESET FB VREF CS SCLK ADN8810 IOUT SDI ADDR0-2 3 FAULT RSN SB AVSS DVSS DGND RSN 1.6V RSN 1.6V D1 FAULT SB INDICATION Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. 1 page ADN8810 TIMING CHARACTERISTICS1, 2 Table 2. Timing Characteristics Parameter Description Min Typ Max Unit fCLK SCLK Frequency 12.5 MHz t1 SCLK Cycle Time 80 ns t2 SCLK Width High 40 ns t3 SCLK Width Low 40 ns t4 CS Low to SCLK High Setup 15 ns t5 CS High to SCLK High Setup 15 ns t6 SCLK High to CS Low Hold 35 ns t7 SCLK High to CS High Hold 20 ns t8 Data Setup 15 ns t9 Data Hold 2 ns t10 CS High Pulsewidth 30 ns t11 RESET Pulsewidth 40 ns t12 CS High to RESET Low Hold 30 ns NOTES 1Guaranteed by design. Not production tested. 2Sample tested during initial release and after any redesign or process change that may affect these parameters. All input signals are measured with tr = tf = 5 ns (10% to 90% of DVDD) and timed from a voltage level of (VIL + VIH)/2. SCLK CS SDI RESET t6 t4 t10 t8 t9 A3* A2 t3 A1 A0 t1 t2 D11 D10 * ADDRESS BIT A3 MUST BE LOGIC LOW Figure 2. Timing Diagram t7 t5 D0 t12 t11 Rev. 0 \| Page 5 of 16 5 Page FUNCTIONAL DESCRIPTION The ADN8810 is a single 12-bit current output D/A converter with a 3-wire SPI interface. Up to eight devices can be independently programmed from the same SPI bus. The full-scale output current is set with two external resistors. The maximum output current can reach 300 mA. Figure 17 shows the functional block diagram of the ADN8810. DVDD AVDD FAULT BIAS SB GEN FAULT DETECTION VREF 12-BIT DAC FB ENCMP 1.5kΩ CS SCLK SDI CONTROL LOGIC 12-BIT DATA LATCH ADDRESS DECODER 1.5kΩ 15kΩ PVDD PVDD IOUT IOUT AVSS RSN DGND ADDR2 ADDR1 ADDR0 RESET DVSS Figure 17. Functional Block Diagram SETTING FULL-SCALE OUTPUT CURRENT Two external resistors set the full-scale output current from the ADN8810. These resistors are equal in value and are labeled RSN in the Functional Block Diagram on the front page. Use 1% or better tolerance resistors to achieve the most accurate output current and the highest output impedance. Equation 1 shows the approximate full-scale output current. The exact output current is determined by the data register code as shown in Equation 2. The variable code is an integer from 0 to 4095, representing the full 12-bit range of the ADN8810. IFS ≈ 4.096 10 × RSN (1) IOUT = Code 1,000 × 1 RSN × ⎜⎛ ⎝ RSN 15k + 0.1⎟⎞ ⎠ (2) REFERENCE VOLTAGE SOURCE The ADN8810 is designed to operate with a 4.096 V reference voltage connected to VREF. The output current is directly proportional to this reference voltage. A low noise precision reference should be used to achieve the best performance. The ADR292, ADR392, or REF198 is recommended. POWER SUPPLIES There are three principal supply current paths through the ADN8810: ADN8810 • AVDD provides power to the analog front end of the ADN8810 including the DAC. Use this supply line to power the external voltage reference. For best performance, AVDD should be low noise. • DVDD provides power for the digital circuitry. This includes the serial interface logic, the SB and RESET logic inputs, and the FAULT output. Tie DVDD to the same supply line used for other digital circuitry. It is not necessary for DVDD to be low noise. • PVDD is the power pin for the output amplifier. It can operate from as low as 3.0 V to minimize power dissipation in the ADN8810. For best performance, PVDD should be low noise. Current is returned through three pins: • AVSS is the return path for both AVDD and PVDD. This pin is connected to the substrate of the die as well as the slug on the bottom of the LFCSP package. For single- supply operation, this pin should be connected to a low noise ground plane. • DVSS returns current from the digital circuitry powered by DVDD. Connect DVSS to the same ground line or plane used for other digital devices in the application. • DGND is the ground reference for the digital circuitry. In a single-supply application, connect DGND to DVSS. For single-supply operation, set AVDD to 5 V, set PVDD from 3.0 V to 5 V, and connect AVSS, AGND, and DGND to ground. SERIAL DATA INTERFACE The ADN8810 uses a serial peripheral interface (SPI) with three input signals: SDI, CLK, and CS. Figure 2 shows the timing diagram for these signals. Data applied to the SDI pin is clocked into the input shift register on the rising edge of CLK. After all 16 bits of the data- word have been clocked into the input shift register, a logic high on CS loads the shift register byte into the ADN8810. If more than 16 bits of data are clocked into the shift register before CS goes high, bits will be pushed out of the register in first-in first- out (FIFO) fashion. The four most significant bits (MSB) of the data byte are checked against the device’s address. If they match, the next 12 bits of the data byte are loaded into the DAC to set the output current. The first bit (MSB) of the data byte must be a logic zero, and the following three bits must correspond to the logic levels on pins ADDR2, ADDR1, and ADDR0, respectively, for the Rev. 0 \| Page 11 of 16 11 Page

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