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PDF ADN2860 Data sheet ( Hoja de datos )
| Número de pieza | ADN2860 | |
| Descripción | 3-Channel Digital Potentiometer with Nonvolatile Memory | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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3-Channel Digital
a
Potentiometer with
Nonvolatile Memory
Preliminary Technical Data
ADN2860
FEATURES
3 Channels: Dual 512-Position
Single 128-Position
25KΩ or 150KΩ Full-Scale Resistance
Low Temperature Coefficient: 35ppm/°C
Nonvolatile Memory Retains Wiper Settings
Permanent Memory Write-Protection
Linear Increment/Decrement
Log taper Increment/Decrement
I2C Compatible Serial Interface
3V to 5V Single Supply Operation
±2.5V Dual Supply Operation
256 Bytes General Purpose User EEPROM
11 Bytes RDAC user EEPROM
GBIC and SFP Compliant EEPROM
100-year Typical Data Retention at TA=55°C
VDD
VSS
GND
SCL
SDA
A0_R
A1_R
A0_E
A1_E
PRB
FUNCTIONAL BLOCK DIAGRAM
256 bytes
USER EEPROM
32 bytes
RDAC EEPROM
RDAC0
REGISTER
I2C
SERIAL
INTERFACE
8 DATA
CONTROL
RDAC1
REGISTER
POWER
ON RESET
COMMAND DECODE LOGIC
ADDRESS DECODE LOGIC
RDAC2
REGISTER
WPB
CONTROL LOGIC
RDAC0
9 bit
RDAC1
9 bit
RDAC2
7 bit
A0
W0
B0
A1
W1
B1
A2
W2
B2
APPLICATIONS
Laser Diode Drivers
Optical Amplifiers
TIA Gain Setting
TEC Controller Temperature Set Points
GENERAL DESCRIPTION
The ADN2860 provides dual 512-position and a single 128-
position digitally controlled variable resistor1 (VR) in a single
4x4mm LFCSP package. This device performs the same
electronic adjustment function as a potentiometer, trimmer, or
variable resistor. Each VR offers a completely programmable
value of resistance between the A terminal and the Wiper or the
B terminal and the Wiper. The fixed A-to-B terminal resistance
of 25kΩ or 250kΩ has a 1% channel-to-channel matching
tolerance and a nominal temperature coefficient of 35ppm/°C.
Wiper position programming, EEPROM reading, and EEPROM
writing is conducted via the standard 2-wire I2C interface.
Previous/Default wiper position settings can be stored in
memory, and refreshed upon system power-up.
Additional features of the ADN2860 include preprogrammed
linear and logarithmic increment/decrement wiper changing, and
actual resistor tolerances are stored in EEPROM so that the
actual end-to-end resistance is known, which is valuable for
calibration in precision applications.
The ADN2860 EEPROM, channel resolution, and package size
conforms to GBIC and SFP specifications. The ADN2860 is
available in a 4x4mm 24-lead LFCSP package. All parts are
guaranteed to operate over the extended industrial temperature
range of –40C to 85°C.
1. The term nonvolatile memory, EEMEM, and EEPROM are used
interchangeably
2. The term programmable resistor, variable resistor, RDAC, and digital
potentiometer are used interchangeably.
REV. PrD
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
Page 1 of 15
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.
1 page  
Preliminary Technical Data
ADN2860ACP PIN CONFIGURATION
ADN2860
PIN DESCRIPTIONS
# Name
1 RESET
2 WP
3 SCL
4 SDA
5 DGND
6 VSS
7 A2
8 W2
9 B2
10 A1
11 W1
12 B1
13 A0
14 W0
15 B0
16 VDD
17 TEST3
18 TEST2
19 TEST1
20 TEST0
21 A1_EE
22 A0_EE
23 AD1
24 AD0
Description
Reset the scratch pad register with current contents of the EEMEM register. Factory defaults midscale before any programming
Write Protect Pin. When active low, WP prevents any changes to the present register contents, except PR and cmd 1 and 8 will refresh the
RDAC register from EEMEM. Execute a NOP instruction before returning to WP high.
Serial Input Register clock pin. Shifts in one bit at a time on positive clock edges.
Serial Data Input Pin. Shifts in one bit at a time on positive clock CLK edges. MSB loaded first.
Ground pin, logic ground reference
Negative Supply. Connect to zero volts for single supply applications.
A terminal of RDAC2.
Wiper terminal of RDAC2
B terminal of RDAC2.
A terminal of RDAC1.
Wiper terminal of RDAC1
B terminal of RDAC1
A terminal of RDAC0.
Wiper terminal of RDAC0.
B terminal of RDAC0
Positive Power Supply Pin.
Test pin 3 (Do Not Connect)
Test pin 2 (Do Not Connect)
Test pin 1 (Do Not Connect)
Test pin 0 (Do Not Connect)
I2C Device Address 1 for EEMEM
I2C Device Address 0 for EEMEM
I2C Device Address 1 for RDAC
I2C Device Address 0 for RDAC
REV. PrD
Page 5 of 15
5 Page 
Preliminary Technical Data
ADN2860
Using Additional Internal Nonvolatile EEPROM
Level Shift for Bi-Directional Communication
The ADN2860 contains additional internal user EEPROM for
saving constants and other data. The user EEPROM I2C
dataword follows the same format as the general purpose
EEPROM memory shown in figures 5 and 6. User EEPROM
memory addresses are shown at the bottom of table 2.
To support the use of multiple EEPROM modules on a single
I2C bus, the ADN2860 features two external addressing pins,
pins 21 and 22 (A1_EE and A0_EE) to manually set the address
of the EEPROM included with the ADN2860. This feature
ensures that the correct EEPROM memory is accessed when
using multiple memory modules on a single I2C bus.
Digital Input/Output Configuration
All digital inputs are ESD protected. Digital inputs are high
impedence and can be driven directly from most digital sources.
Active at logic low, RESET and WP should be biased to VDD if
they are not used. There are no internal pull-up resistors present
on any of the digital input pins of the ADN2860. As a result,
pull-up resistors are needed if these functions are not used.
While most old systems may be operating at one voltage, a new
component may be optimized at another. When two systems
transmit the same signal at two different voltages, proper level
shifting is required.
In some instances, for example, a 3.3V EEPROM memory
module may be used along with a 5V digital potentiometer. A
level shifting scheme is required in order to enable bi-directional
communication between the two devices.
VDD1 = 3.3V
VDD2 = 5V
SDA1
SCL1
Rp
3. 3V
E2PROM
Rp
G
S
Rp
G
D
M1 S
D
M2
Rp
5V
ADN2860
SD A2
SC L2
ESD protection of the digital inputs is shown in figure 13.
VDD
INPUT
300 Ω
WP
Figure 15. Level Shifting for different voltage devices on an I2C
bus
Figure 15 shows one of many possible techniques to properly
level shift signals between two devices. M1 and M2 can be N-
channel FETs (2N7002). If VDD falls below 2.5V, M1 and M2
should be low threshold N-channel FETs (FDV301N).
Terminal Voltage Operation Range
GND
Figure 13. Equivalent WP Input Protection
The ADN2860 positive VDD and negative VSS power supply
inputs define the boundary conditions for proper 2-terminal
programmable resistance operation. Supply signals on terminals
W and B that exceed VDD or VSS will be clamped by the internal
forward biased diodes of the ADN2860.
Multiple Devices On One Bus
Figure 14 shows four ADN2860 devices on the same serial bus.
Each has a different slave address since the state of their AD0
and AD1 pins are different. This allows each RDAC within each
device to be written to or read from independently.
+5 V
Rp Rp
M A S TE R
S DA SCL
AD 1
AD 0
VDD
SDA S CL
A D1
A D0
VD D
SDA S CL
A D1
A D0
VDD
S DA SCL
AD 1
AD 0
SDA
SCL
Figure 14. Multiple ADN2860 Devices on a Single Bus
VDD
W
B
VSS
Figure 16. Maximum Terminal Voltages Set by VDD & VSS
The ground pin of the ADN2860 device is primarily used as a
digital ground reference, which needs to be tied to the common
ground of the PCB. The digital input control signals to the
ADN2860 must be referenced to the device ground pin, and
satisfy the logic levels defined in the specification table of this
datasheet.
REV. PrD
An internal level shift circuit insures that the common mode
voltage range of the 2-terminals extends from VSS to VDD
Page 11 of 15
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet ADN2860.PDF ] | |
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