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PDF ADMCF340 Data sheet ( Hoja de datos )
| Número de pieza | ADMCF340 | |
| Descripción | DashDSPTM 64-Lead Flash Mixed-Signal DSP with Enhanced Analog Front End | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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a DashDSPTM 64-Lead Flash Mixed-Signal DSP
with Enhanced Analog Front End
ADMCF340
TARGET APPLICATIONS
Refrigerator and Air Conditioner Compressors,
Washing Machines
Industrial Variable Speed Drives, HVAC
MOTOR TYPES
Permanent Magnet Synchronous Motors (PMSM),
Brushless DC Motors (BDCM), AC Induction Motors
(ACIM), Switched Reluctance Motors (SRM)
FEATURES
20 MHz Fixed-Point DSP Core
Single Cycle Instruction Execution (50 ns)
ADSP-21xx Family Code Compatibility
Independent Computational Units
ALU
Multiplier/Accumulator
Barrel Shifter
Multifunction Instructions
Single Cycle Context Switch
Powerful Program Sequencer
Zero Overhead Looping
Conditional Instruction Execution
Two Independent Data Address Generators
Memory Configuration
512 ؋ 16-Bit Data Memory RAM
512 ؋ 24-Bit Program Memory RAM
4K ؋ 24-Bit Program Memory ROM
4K ؋ 24-Bit Total Program FLASH Memory
Three Independent FLASH Memory Sectors
3584 ؋ 24-Bit, 256 ؋ 24-Bit, 256 ؋ 24-Bit
Low Cost Pin-Compatible ROM Option
16-Bit Watchdog Timer
Programmable 16-Bit Internal Timer with Prescaler
Two Double Buffered Serial Ports with SPI Mode
Support
Integrated Power On Reset Function
Three Phase 16-Bit PWM Generation Unit
16-Bit Center-Based PWM Generator
Programmable PWM Pulsewidth
Edge Resolution of 50 ns
Programmable Narrow Pulse Deletion
153 Hz Minimum Switching Frequency
Double/Single Update Mode Control
Individual Enable and Disable for Each PWM
Output
High Frequency Chopping Mode for
Transformer-Coupled Gate Drives
(continued on page 8)
FUNCTIONAL BLOCK DIAGRAM
ADSP-21xx BASE
ARCHITECTURE
DATA
ADDRESS
GENERATORS
DAG 1 DAG 2
PROGRAM
SEQUENCER
MEMORY BLOCK
PROGRAM
ROM
4K ؋ 24
PROGRAM
RAM
512 ؋ 24
PROGRAM
FLASH
4K ؋ 24
DATA
MEMORY
512 ؋ 16
PROGRAM MEMORY ADDRESS
MOTOR CONTROL PERIPHERALS
ADC SUBSYSTEM
10
VREF
2.5V
ANALOG
INPUTS
3
ISENSE AMP
AND TRIP
SHA
TIMERS
6
16-BIT
THREE-
PHASE
PWM
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
ARITHMETIC UNITS
ALU MAC SHIFTER
POR
TIMER
SERIAL PORT
SPORT 0
SPORT 1
7
2 ؋ 16-BIT
PIO AUX
PWM
25 2
WATCH-
DOG
TIMER
DashDSP is a trademark of Analog Devices, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accu-
rate and reliable. However, no responsibility is assumed by
Analog Devices for its use, nor for any infringements of patents
or other rights of third parties that may result from its use. No
license is granted by implication or otherwise under any patent
or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002
1 page  
TIMING PARAMETERS
Parameter
Serial Ports
Timing Requirements:
tSCK SCLK Period
tSCS DR/TFS/RFS Setup before SCLK Low
tSCH DR/TFS/RFS Hold after SCLK Low
tSCP SCLKIN Width
Switching Characteristics:
tCC
tSCDE
tSCDV
tRH
tRD
tSCDH
CLKOUT High to SCLKOUT
SCLK High to DT Enable
SCLK High to DT Valid
TFS/RFSOUT Hold after SCLK High
TFS/RFSOUT Delay from SCLK High
DT Hold after SCLK High
tSCDD
tTDE
tTDV
SCLK High to DT Disable
TFS (Alt) to DT Enable
TFS (Alt) to DT Valid
tRDV RFS (Multichannel, Frame Delay Zero) to DT Valid
Specifications subject to change without notice.
ADMCF340
Min Max
Unit
100
15
20
40
0.25 TCK
0
0
0
0
0.25 TCK + 20
30
30
30
25
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLKOUT
SCLK
DR
RFSIN
TFSIN
RFSOUT
TFSOUT
DT
TFS
(ALTERNATE
FRAME MODE)
RFS
(MULTICHANNEL MODE,
FRAME DELAY 0 [MFD = 0])
tCC tCC
tSCS tSCH
t SCK
t SCP
t SCP
t RD
t RH
t SCDE
t SCDV
t TDE
t TDV
t SCDH
t SCDD
t RDV
Figure 2. Serial Port Timing
REV. 0
–5–
5 Page 
ADMCF340
FLASH MEMORY SUBSYSTEM
The ADMCF340 has 4K × 24-bit of user-programmable, nonvola-
tile flash memory. A flash programming utility is provided with the
development tools that performs the basic device programming
operations: erase, program, and verify.
The flash memory array is portioned into three asymmetrically
sized sectors of 256 words, 256 words, and 3,584 words, labeled
Sector 0, Sector 1, and Sector 2, respectively. These sectors are
mapped into external program memory address space.
Four flash memory interface registers are connected to the DSP.
These 16-bit registers are mapped into the register area of data
memory space. They are named Flash Memory Control Register
(FMCR), Flash Memory Address Register (FMAR), Flash
Memory Data Register Low (FMDRL), and Flash Memory Data
Register High (FMDRH). These registers are diagrammed later in
this data sheet. They are used by the flash memory programming
utility. The user program may read these registers but should not
modify them directly. The flash programming utility provides a
complete interface to the flash memory.
Note: From the point of view of 2171 core, the flash memory
is placed externally. It means the core accesses them through
an external memory interface that multiplexes the program
memory and data memory buses into a single external bus.
Therefore, if more than one external transfer must be made in
the same instruction, there will be at least an overhead cycle
required. For more details, see Application Note ANF32X-65
Guidelines to Transfer Code from ADMCF32x to ADMC32x.
Special Flash Registers
The flash module has four nonvolatile 8-bit registers called Special
Flash Registers (SFRs) that are accessible independently of
the main flash array via the flash programming utility. These
registers are for general-purpose, nonvolatile storage. When
erased, the Special Flash Registers contain all “0s.” To read
Special Flash Registers from the user program, call the read_reg
routine contained in the ROM. Refer to the ADMCF34x DSP
Motor Controller Developers’ Reference Manual for an example.
Boot-from-Flash Code
A security feature is available in the form of a code that when set
causes the processor to execute the program in flash memory at
power-up or reset. In this mode, the flash programming utility
and debugger are unable to communicate with the ADMCF340.
Consequently, the contents of the flash memory can be neither
programmed nor read.
The boot-from-flash code may be set via the flash programming
utility when the user’s program is thoroughly tested and loaded
into flash program memory at Address 0x2200. The user’s pro-
gram must contain a mechanism for clearing the boot-from-flash
code if reprogramming the flash memory is desired. The only
way to clear boot-from-flash is from within the user program, by
calling the flash_init or auto_erase_reg routines that are included in the
ROM. The user program must be signaled in some way to call the
necessary routine to clear the boot-from-flash code. An example
would be to detect a high level on a PIO pin during startup initial-
ization and then call the flash_init or auto-erase-reg routine.
The flash_init routine will erase the entire user program in
flash memory before clearing the boot-from-flash code, thus
ensuring the security of the user program. If security is not a
concern, the auto_erase_reg routine can be used to clear the
boot-from-flash code while leaving the user program intact.
Refer to the ADMCF34x DSP Motor Controller Developers’
Reference Manual for further instructions and an example of
using the boot-from-flash code.
FLASH PROGRAM BOOT SEQUENCE
On power-up or reset, the processor begins instruction execution
at Address 0x0800 of internal program ROM. The ROM monitor
program that is located there checks the boot-from-flash code. If
that code is set, the processor jumps to location 0x2200 in external
flash program memory, where it expects to find the user’s
application program.
If the boot-from-flash code is not set, the monitor attempts to
boot from an external device as described in the ADMCF34x
DSP Motor Controller Developers’ Reference Manual.
SYSTEM INTERFACE
Figure 4 shows a basic system configuration for the ADMCF340
with an external crystal.
CLKOUT XTAL
22pF
10MHz
CLKIN
ADMCF340
22pF
RESET
Figure 4. Basic System Configuration
Clock Signals
The ADMCF340 can be clocked either by a crystal or a TTL
compatible clock signal. For normal operation, the CLKIN
input cannot be halted, changed during operation, or operated
below the specified minimum frequency. If an external clock is
used, it should be a TTL compatible signal running at half the
instruction rate. The signal is connected to the CLKIN pin of
the ADMCF340. In this mode, with an external clock signal,
the XTAL Pin must be left unconnected. The ADMCF340 uses
an input clock with a frequency equal to half the instruction
rate; a 10 MHz input clock yields a 50 ns processor cycle (which is
equivalent to 20 MHz). Normally, instructions are executed
in a single processor cycle. All device timing is relative to the
internal instruction rate that is indicated by the CLKOUT
signal when enabled.
Because the ADMCF340 includes an on-chip oscillator feedback
circuit, an external crystal may be used instead of a clock source,
as shown in Figure 2. The crystal should be connected across the
CLKIN and XTAL Pins with two capacitors (see Figure 2). A
parallel-resonant, fundamental frequency, microprocessor-grade
crystal should be used. A clock output signal (CLKOUT) is
generated by the processor at the processor’s cycle rate of twice
the input frequency.
REV. 0
–11–
11 Page | ||
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| PDF Descargar | [ Datasheet ADMCF340.PDF ] | |
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