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PDF ADMC401BST Data sheet ( Hoja de datos )
| Número de pieza | ADMC401BST | |
| Descripción | Single-Chip/ DSP-Based High Performance Motor Controller | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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a
Single-Chip, DSP-Based
High Performance Motor Controller
ADMC401
FEATURES
26 MIPS Fixed-Point DSP Core
Single Cycle Instruction Execution (38.5 ns)
ADSP-21xx Family Code Compatible
16-Bit Arithmetic and Logic Unit (ALU)
Single Cycle 16-Bit ؋ 16-Bit Multiply and Accumulate
Into 40-Bit Accumulator (MAC)
32-Bit Shifter (Logical and Arithmetic)
Multifunction Instructions
Single Cycle Context Switch
Zero Overhead Looping
Conditional Instruction Execution
Two Independent Data Address Generators
Memory Configuration
2K ؋ 24-Bit Internal Program Memory RAM
2K ؋ 24-Bit Internal Program Memory ROM
1K ؋ 16-Bit Internal Data Memory RAM
14-Bit Address Bus and 24-Bit Data Bus for External
Memory Expansion
High Resolution Multichannel ADC
12-Bit Pipeline Flash Analog-to-Digital Converter
Eight Dedicated Analog Inputs
Simultaneous Sampling Capability
All Eight Inputs Converted in <2 s
4.0 V p-p Input Voltage Range
PWM Synchronized or External Convert Start
Internal or External Voltage Reference
Out-of-Range Detection
Voltage Reference
Internal 2.0 V ؎ 2.0% Voltage Reference
Three-Phase 16-Bit PWM Generation Unit
Programmable Switching Frequency, Dead Time and
Minimum Pulsewidth
Edge Resolution of 38.5 ns
One or Two Updates per Switching Period
Hardware Polarity Control
Individual Enable/Disable of Each Output
High Frequency Chopping Mode
Dedicated Shutdown Pin (PWMTRIP)
Additional Shutdown Pins in I/O System
High Output Sink and Source Capability (10 mA)
Incremental Encoder Interface Unit
Quadrature Rates to 17.3 MHz
Programmable Filtering of Encoder Inputs
Alternative Frequency and Direction Mode
Two Registration Inputs to Latch Count Value
Optional Hardware Reset of Counter
Single North Marker Mode
Count Error Monitor Function
Dedicated 16-Bit Loop Timer (Periodic Interrupts)
Companion Encoder Event (1/T) Timer
(Continued on Page 14)
FUNCTIONAL BLOCK DIAGRAM
EXTERNAL
ADDRESS
BUS
EXTERNAL
DATA
BUS
26 MIPS DSP CORE
DATA
ADDRESS
GENERATORS
DAG 1 DAG 2
PROGRAM
SEQUENCER
PM
ROM
2K ؋ 24
PM
RAM
2K ؋ 24
MEMORY
DM
RAM
1K ؋ 16
MOTOR CONTROL
PERIPHERALS
WATCH-
DOG
TIMER
POWER-
ON
RESET
INTERRUPT
CONTROLLER
ENCODER
INTERFACE
EVENT
CAPTURE
UNIT
DIGITAL
I/O
UNIT
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
ARITHMETIC UNITS
ALU MAC SHIFTER
SERIAL PORTS
INTERVAL
SPORT 0 SPORT 1
TIMER
2 CHANNEL
AUXILIARY
PWM
8 CHANNEL
12-BIT ADC
PRECISION
VOLTAGE
REFERENCE
16-BIT
PWM
GENERATION
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
1 page  
ADMC401
Parameter
Min Max Unit
Clock Signals
tCK is defined as 0.5tCKI. The ADMC401 uses an input clock
with a frequency equal to half the instruction rate; a 13 MHz
clock (which is equivalent to 76.9 ns) yields a 38.5 ns processor
cycle (equivalent to 26 MHz). tCK values within the range of
0.5tCKI period should be substituted for all relevant timing
parameters to obtain specification value.
Example: tCKH = 0.5tCK – 10 ns = 0.5 (38.5 ns) – 10 ns = 9.25 ns.
Timing Requirements:
tCKI
tCKIL
tCKIH
CLKIN Period
CLKIN Width Low
CLKIN Width High
Switching Characteristics:
76.9 150 ns
20 ns
20 ns
tCKL
tCKH
tCKOH
CLKOUT Width Low
CLKOUT Width High
CLKIN High to CLKOUT High
Control Signals
0.5tCK – 10
0.5tCK – 10
0
20
ns
ns
ns
Timing Requirement:
tRSP RESET Width Low
5tCK1
ns
PWM Shutdown Signals
Timing Requirements:
tPWMTPW
tPIOPWM
PWMTRIP Width Low
PIO Width Low
ADC Signals
tCK
2tCK
ns
ns
Timing Requirements:
tCSI Internal Convert Start Width High
tCSE External Convert Start Width High
2tCK
2tCK
ns
ns
NOTE
1Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal
oscillator start-up time).
CLKIN
CLKOUT
t CKI
t CKIH
t CKIL
t CKOH
t CKH
t CKL
Figure 1. Clock Signals
REV. B
–5–
5 Page 
ADMC401
POWER DISSIPATION
To determine total power dissipation in a specific application,
the following equation should be applied for each output:
C × VDD2 × f
C = load capacitance, f = output switching frequency.
Example:
In an application where external data memory is used and no
other outputs are active, power dissipation is calculated as
follows:
Assumptions:
• External data memory is accessed every cycle with 50% of the
address pins switching.
• External data memory writes occur every other cycle with
50% of the data pins switching.
• Each address and data pin has a 10 pF total load at the pin.
• The application operates at VDD = 5.0 V and tCK = 38.5 ns.
Total Power Dissipation = PINT + (C × VDD2 × f)
PINT = VDD × (IDD Digital + IDD Analog)
(C × VDD2 × f) is calculated for each output:
# of
Pins ؋ C
Address, DMS
Data Output, WR
RD
CLKOUT
8
9
1
1
× 10 pF
× 10 pF
× 10 pF
× 10 pF
؋ VDD2 ؋ f
× 52 V
× 52 V
× 52 V
× 52 V
× 26 MHz
× 13 MHz
× 13 MHz
× 26 MHz
= 52.00 mW
= 29.25 mW
= 3.25 mW
= 6.50 mW
91.00 mW
Total power dissipation for this example is PINT + 91 mW.
TEST CONDITIONS
Output Disable Time
Output pins are considered to be disabled when they have
stopped driving and started a transition from the measured
output high or low voltage to a high impedance state. The out-
put disable time (tDIS) is the difference of tMEASURED and tDECAY,
as shown in the Output Enable/Disable diagram. The time is the
interval from when a reference signal reaches a high or low
voltage level to when the output voltages have changed by 0.5 V
from the measured output high or low voltage. The decay time,
tDECAY, is dependent on the capacitative load, CL, and the cur-
rent load, iL, on the output pin. It can be approximated by the
following equation:
from which
tDECAY
=
CL
× 0.5 V
IL
tDIS = tMEASURED − tDECAY
is calculated. If multiple pins (such as the data bus) are dis-
abled, the measurement value is that of the last pin to stop
driving.
INPUT
3.0V
1.5V
0.0V
OUTPUT
2.0V
1.5V
0.3V
Figure 7. Voltage Reference Levels for AC Measure-
ments (Except Output Enable/Disable)
Output Enable Time
Output pins are considered to be enabled when that have made
a transition from a high-impedance state to when they start
driving. The output enable time (tENA) is the interval from when
a reference signal reaches a high or low voltage level to when
the output has reached a specified high or low trip point, as
shown in the Output Enable/Disable diagram. If multiple pins
(such as the data bus) are enabled, the measurement value is
that of the first pin to start driving.
REFERENCE
SIGNAL
tMEASURED
VOH
(MEASURED)
tDIS
OUTPUT
VOL
(MEASURED)
VOH (MEASURED) – 0.5V
VOL (MEASURED) +0.5V
tDECAY
tENA
2.0V
1.0V
VOH
(MEASURED)
VOL
(MEASURED)
OUTPUT STOPS
DRIVING
OUTPUT STARTS
DRIVING
HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE
THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1.5V.
Figure 8. Output Enable/Disable
IOL
TO
OUTPUT
PIN
50pF
+1.5V
IOH
Figure 9. Equivalent Device Loading for AC Measure-
ments (Including All Fixtures)
REV. B
–11–
11 Page | ||
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| PDF Descargar | [ Datasheet ADMC401BST.PDF ] | |
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