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PDF ADMC331-PB Data sheet ( Hoja de datos )
| Número de pieza | ADMC331-PB | |
| Descripción | Single Chip DSP Motor Controller | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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a
TARGET APPLICATIONS
Washing Machines, Refrigerator Compressors, Fans,
Pumps, Industrial Variable Speed Drives
FEATURES
26 MIPS Fixed-Point DSP Core
Single Cycle Instruction Execution (38.5 ns)
ADSP-2100 Family Code Compatible
Independent Computational Units
ALU
Multiplier/Accumulator
Barrel Shifter
Multifunction Instructions
Single Cycle Context Switch
Powerful Program Sequencer
Zero Overhead Looping
Conditional Instruction Execution
Two Independent Data Address Generator
Memory Configuration
2K ؋ 24-Bit Program Memory RAM
2K ؋ 24-Bit Program Memory ROM
1K ؋ 16-Bit Data Memory RAM
Three-Phase 16-Bit PWM Generator
16-Bit Center-Based PWM Generator
Programmable Deadtime and Narrow Pulse Deletion
Single Chip DSP
Motor Controller
ADMC331
Edge Resolution to 38.5 ns
198 Hz Minimum Switching Frequency
Double/Single Duty Cycle Update Mode Control
Programmable PWM Pulsewidth
Suitable for AC Induction and Synchronous Motors
Special Signal Generation for Switched Reluctance
Motors
Special Crossover Function for Brushless DC Motors
Individual Enable and Disable for all PWM Outputs
High Frequency Chopping Mode for Transformer
Coupled Gate Drives
Hardwired Polarity Control
External PWMTRIP Pin
Seven Analog Input Channels
Acquisition Synchronized to PWM Switching
Frequency
Conversion Speed Control
24 Bits of Digital I/O Port
Bit Configurable as Input or Output
Change of State Interrupt Support
Two 8-Bit Auxiliary PWM Timers
Synchronized Analog Output
Programmable Frequency
0% to 100% Duty Cycle
FUNCTIONAL BLOCK DIAGRAM
(Continued on page 7)
ADSP-2100 BASE
ARCHITECTURE
DATA
ADDRESS
GENERATORS
DAG 1 DAG 2
PROGRAM
SEQUENCER
PROGRAM
ROM
2K ؋ 24
PROGRAM
RAM
2K ؋ 24
MEMORY
DATA
RAM
1K ؋ 16
WATCH-
DOG
TIMER
24-BIT
PIO
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
ARITHMETIC UNITS
ALU MAC SHIFTER
SERIAL PORTS
SPORT 0 SPORT 1
TIMER
2 ؋ 8 BIT
AUX
PWM
7
ANALOG
INPUTS
16-BIT
3-PHASE
PWM
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
1 page  
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage (VDD) . . . . . . . . . . . . . . . . . . –0.3 V to +7.0 V
Supply Voltage (AVDD) . . . . . . . . . . . . . . . . . –0.3 V to +7.0 V
Input Voltage . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Output Voltage Swing . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Operating Temperature Range (Ambient) . . . – 40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (5 sec) . . . . . . . . . . . . . . . . . . . . . .+280°C
ADMC331
*Stresses greater than those listed above may cause permanent damage to the
device. These are stress ratings only; functional operation of the device at these
or any other conditions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Model
ADMC331BST
ADMC331-ADVEVALKIT
ADMC331-PB
Temperature
Range
–40°C to +85°C
ORDERING GUIDE
Instruction
Rate
26 MHz
Package
Description
80-Lead Plastic Thin Quad Flatpack (TQFP)
Development Tool Kit
Evaluation/Processor Board
Package
Option
ST-80
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADMC331 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. B
–5–
5 Page 
Utility
PER_RST
UMASK
PUT_VECTOR
SMASK
ADMC_COS
ADMC_SIN
ARCTAN
RECIPROCAL
SQRT
LN
LOG
FLTONE
FIXONE
FPA
FPS
FPM
FPD
FPMACC
PARK
REV_CLARK
FOR_CLARK
COS64
ONE_BY_X
SDIVQINT
SDIVQ
Table IV. ROM Utilities
Address
0x07F1
0x0DED
0x0DF4
0x0E06
0x0E26
0x0E2D
0x0E43
0x0E65
0x0E7B
0x0EB5
0x0EB8
0x0ED4
0x0ED9
0x0EDD
0x0EEC
0x0EFC
0x0F05
0x0F26
0x0F48
0x0F5C
0x0F72
0x0F80
0x0FCO
0x0FD0
0x0FD9
Function
Reset Peripherals.
Limits Unsigned Value to
Given Range.
Facilitates User Setup of
Vector Table.
Limits Signed Value to Given
Range.
Cosine Function.
Sine Function.
Arctangent Function.
Reciprocal (1/×) Function.
Square Root Function.
Natural Logarithm Function.
Logarithm (Base 10) Function.
Fixed Pt. to Float Conversion.
Float to Fixed Pt. Conversion.
Floating Pt. Addition.
Floating Pt. Subtraction.
Floating Pt. Multiplication.
Floating Pt. Division.
Floating Pt. Multiply/Accumulate.
Forward/Reverse Park
Transformation.
Reverse Clark Transformation.
Forward Clark Transformation.
64 Pt. COS Table.
16 Pt. 1/× Table.
Unsigned Single Precision
Division (Integer).
Unsigned Single Precision
Division (Fractional).
SYSTEM INTERFACE
Figure 4 shows a basic system configuration for the ADMC331,
with an external crystal and serial E2PROM for boot loading of
program and data memory RAM.
CLKOUT
XTAL
CLKIN
ADMC331
DR1A
RESET
SCLK1
RFS1/ SROM
13 MHz
DATA
CLK
RESET
SERIAL
E2PROM
Figure 4. Basic System Configuration
ADMC331
Clock Signals
The ADMC331 can be clocked by either a crystal or a TTL-
compatible clock signal. The CLKIN input cannot be halted,
changed during operation nor operated below the specified
minimum frequency during normal operation. If an external
clock is used, it should be a TTL-compatible signal running at
half the instruction rate. The signal is connected to the CLKIN
pin of the ADMC331. In this mode, with an external clock
signal, the XTAL pin must be left unconnected. The ADMC331
uses an input clock with a frequency equal to half the instruc-
tion rate; a 13 MHz input clock yields a 38.5 ns processor cycle
(which is equivalent to 26 MHz). Normally, instructions are
executed in a single processor cycle. All device timing is
relative to the internal instruction rate, which is indicated by
the CLKOUT signal.
Because the ADMC331 includes an on-chip oscillator feedback
circuit, an external crystal may be used instead of a clock
source, as shown in Figure 4. The crystal should be connected
across the CLKIN and XTAL pins, with two capacitors as
shown in Figure 4. A parallel-resonant, fundamental frequency,
microprocessor-grade crystal should be used. A clock output
signal (CLKOUT) is generated by the processor at the processor’s
cycle rate of twice the input frequency. This output can be
enabled and disabled by the CLKODIS bit of the SPORT0
Autobuffer Control Register, DM[0x3FF3]. However, extreme
care must be exercised when using this bit since disabling
CLKOUT effectively disables all motor control peripherals,
except the watchdog timer.
Reset
The RESET signal initiates a master reset of the ADMC331.
The RESET signal must be asserted during the power-up se-
quence to assure proper initialization. RESET during initial
power-up must be held long enough to allow the internal clock
to stabilize. If RESET is activated any time after power-up, the
clock continues to run and does not require stabilization time.
The power-up sequence is defined as the total time required for
the crystal oscillator circuit to stabilize after a valid VDD is ap-
plied to the processor, and for the internal phase-locked loop
(PLL) to lock onto the specific crystal frequency. A minimum
of 2000 CLKIN cycles ensures that the PLL has locked, but
does not include the crystal oscillator start-up time. During this
power-up sequence, the RESET signal should be held low. On
any subsequent resets, the RESET signal must meet the mini-
mum pulsewidth specification, tRSP.
If an RC circuit is used to generate the RESET signal, the use of
an external Schmitt trigger is recommended.
The master reset sets all internal stack pointers to the empty
stack condition, masks all interrupts, initializes DSP core regis-
ters and performs a full reset of all of the motor control periph-
erals. When the RESET line is released, the first instruction is
fetched from internal program memory ROM at location 0x0800.
The internal monitor code at this location then commences the
boot-loading sequence over the serial port, SPORT1. A soft-
ware controlled full peripheral reset is achieved by toggling the
DSP FL2 flag from 1 to 0 to 1 again.
REV. B
–11–
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