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PDF ADMC326TR Data sheet ( Hoja de datos )
| Número de pieza | ADMC326TR | |
| Descripción | 28-Lead ROM-Based DSP Motor Controller | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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a
TARGET APPLICATIONS
Washing Machines, Refrigerator Compressors, Fans,
Pumps, Industrial Variable Speed Drives, Automotive
MOTOR TYPES
AC Induction Motors
Permanent Magnet Synchronous Motors (PMSM)
Brushless DC Motors (BDCM)
FEATURES
20 MIPS Fixed-Point DSP Core
Single Cycle Instruction Execution (50 ns)
ADSP-21xx Family Code Compatible
Independent Computational Units
ALU
Multiplier/Accumulator
Barrel Shifter
Multifunction Instructions
Single Cycle Context Switch
Powerful Program Sequencer
Zero Overhead Looping
Conditional Instruction Execution
Two Independent Data Address Generators
Memory Configuration
512 ؋ 24-Bit Program Memory RAM
4K ؋ 24-Bit Program Memory ROM
512 ؋ 16-Bit Data Memory RAM
Three-Phase 16-Bit PWM Generator
16-Bit Center-Based PWM Generator
Programmable Dead Time and Narrow Pulse Deletion
28-Lead ROM-Based
DSP Motor Controller
ADMC326
Edge Resolution to 50 ns
150 Hz Minimum Switching Frequency
Double/Single Duty Cycle Update Mode Control
Programmable PWM Pulsewidth
Special Crossover Function for Brushless DC Motors
Individual Enable and Disable for Each PWM Output
High Frequency Chopping Mode for Transformer
Coupled Gate Drives
External PWMTRIP Pin
Integrated ADC Subsystem
Six Analog Inputs
Acquisition Synchronized to PWM Switching Frequency
Internal Voltage Reference
9-Pin Digital I/O Port
Bit Configurable as Input or Output
Change of State Interrupt Support
Two 8-Bit Auxiliary PWM Timers
Synthesized Analog Output
Programmable Frequency
0% to 100% Duty Cycle
Two Programmable Operational Modes
Independent Mode/Offset Mode
16-Bit Watchdog Timer
Programmable 16-Bit Internal Timer with Prescaler
Double Buffered Synchronous Serial Port
Hardware Support for UART Emulation
Integrated Power-On Reset Function
28-Lead SOIC or PDIP Package Options
FUNCTIONAL BLOCK DIAGRAM
ADSP-2100 BASE
ARCHITECTURE
DATA
ADDRESS
GENERATORS
DAG 1 DAG 2
PROGRAM
SEQUENCER
PROGRAM
ROM
4K ؋ 24
PROGRAM
RAM
512 ؋ 24
MEMORY
BLOCK
DATA
MEMORY
512 ؋ 16
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
ARITHMETIC UNITS
ALU MAC SHIFTER
POR
TIMER
VREF
6
ANALOG
INPUTS
16-BIT
3-PHASE
PWM
SERIAL PORT
SPORT1
9-BIT
PIO
2 ؋ 8-BIT
AUX
PWM
WATCH-
DOG
TIMER
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
1 page  
Parameter
Serial Ports
Timing Requirements:
tSCK SCLK Period
tSCS DR/TFS/RFS Setup before SCLK Low
tSCH DR/TFS/RFS Hold after SCLK Low
tSCP SCLKIN Width
Switching Characteristics:
tCC CLKOUT High to SCLKOUT
tSCDE
SCLK High to DT Enable
tSCDV
tRH
SCLK High to DT Valid
TFS/RFSOUT Hold after SCLK High
tRD
tSCDH
tSCDD
TFS/RFSOUT Delay from SCLK High
DT Hold after SCLK High
SCLK High to DT Disable
tTDE
tTDV
TFS (Alt) to DT Enable
TFS (Alt) to DT Valid
tRDV RFS (Multichannel, Frame Delay Zero) to DT Valid
Specifications subject to change without notice.
ADMC326
Min Max
Unit
100
15
20
40
0.25 tCK
0
0
0
0
0.25 tCK + 20
30
30
30
25
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLKOUT
SCLK
DR
RFSIN
TFSIN
RFSOUT
TFSOUT
DT
TFS
(ALTERNATE
FRAME MODE)
RFS
(MULTICHANNEL MODE,
FRAME DELAY 0 [MFD = 0])
tCC tCC
tSCS tSCH
t SCK
t SCP
t SCP
t RD
t RH
t SCDE
t SCDV
t TDE
t TDV
t SCDH
t SCDD
t RDV
Figure 2. Serial Port Timing
REV. A
–5–
5 Page 
ADMC326
state. Because this hardware shutdown mechanism is asynchro-
nous, and the associated PWM disable circuitry does not use
clocked logic, the PWM will shut down even if the DSP clock is
not running. The PWM system may also be shut down from
software by writing to the PWMSWT register.
Status information about the PWM system of the ADMC326 is
available to the user in the SYSSTAT register. In particular, the
state of PWMTRIP is available, as well as a status bit that indi-
cates whether operation is in the first half or the second half of
the PWM period.
A functional block diagram of the PWM controller is shown in
Figure 6. The generation of the six output PWM signals on pins
AH to CL is controlled by four important blocks:
• The three-phase PWM timing unit, which is the core of the
PWM controller, generates three pairs of complemented and
dead-time-adjusted center-based PWM signals.
• The output control unit allows the redirection of the outputs
of the three-phase timing unit for each channel to either the
high side or the low side output. In addition, the output con-
trol unit allows individual enabling/disabling of each of the six
PWM output signals.
• The GATE drive unit provides the high chopping frequency
and its subsequent mixing with the PWM signals.
• The PWM shutdown controller manages the three PWM
shutdown modes (via the PWMTRIP pin, the analog block or
the PWMSWT register) and generates the correct RESET signal
for the Timing Unit.
• The PWM controller is driven by a clock at the same frequency
as the DSP instruction rate, CLKOUT, and is capable of
generating two interrupts to the DSP core. One interrupt is
generated on the occurrence of a PWMSYNC pulse, and the
other is generated on the occurrence of any PWM shutdown
action.
PWM CONFIGURATION
REGISTERS
PWMTM (15...0)
PWMDT (9...0)
PWMPD (15...0)
PWMSYNCWT (7...0)
MODECTRL (6)
PWM DUTY CYCLE
REGISTERS
PWMCHA (15...0)
PWMCHB (15...0)
PWMCHC (15...0)
Three-Phase Timing Unit
The 16-bit three-phase timing unit is the core of the PWM con-
troller and produces three pairs of pulsewidth modulated signals
with high resolution and minimal processor overhead. There are
four main configuration registers (PWMTM, PWMDT, PWMPD
and PWMSYNCWT) that determine the fundamental charac-
teristics of the PWM outputs. In addition, the operating mode
of the PWM (single or double update mode) is selected by Bit 6
of the MODECTRL register. These registers, in conjunction with
the three 16-bit duty cycle registers (PWMCHA, PWMCHB and
PWMCHC), control the output of the three-phase timing unit.
PWM Switching Frequency: PWMTM Register
The PWM switching frequency is controlled by the PWM
period register, PWMTM. The fundamental timing unit of
the PWM controller is tCK = 1/fCLKOUT where fCLKOUT is the
CLKOUT frequency (DSP instruction rate). Therefore, for a
20 MHz CLKOUT, the fundamental time increment is 50 ns.
The value written to the PWMTM register is effectively the
number of tCK clock increments in half a PWM period. The
required PWMTM value is a function of the desired PWM
switching frequency (fPWM) and is given by:
PWMTM
=
fCLKOUT
2 × fPWM
=
fCLKIN
fPWM
Therefore, the PWM switching period, TS, can be written as:
TS = 2 × PWMTM × tCK
For example, for a 20 MHz CLKOUT and a desired PWM
switching frequency of 10 kHz (TS = 100 µs), the correct value
to load into the PWMTM register is:
PWMTM
=
2
20 × 106
× 10 × 103
1000
=
0x3E8
PWMSEG (8...0)
PWMGATE (9...0)
THREE-PHASE
PWM TIMING
UNIT
CLK SYNC RESET
PWMSYNC
TO INTERRUPT
CONTROLLER
PWMTRIP
OUTPUT
CONTROL
UNIT
SYNC
OR
GATE
DRIVE
UNIT
CLK
AH
AL
BH
BL
CH
CL
CLKOUT
PWMTRIP
PWMSWT (0)
PWM SHUTDOWN CONTROLLER
REV. A
Figure 6. Overview of the PWM Controller of the ADMC326
–11–
11 Page | ||
| Páginas | Total 31 Páginas | |
| PDF Descargar | [ Datasheet ADMC326TR.PDF ] | |
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