|
|
PDF ADM8694 Data sheet ( Hoja de datos )
| Número de pieza | ADM8694 | |
| Descripción | Microprocessor Supervisory Circuits | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de ADM8694 (archivo pdf) en la parte inferior de esta página. Total 20 Páginas | ||
|
No Preview Available !
Microprocessor
Supervisory Circuits
ADM8690/ADM8691/ADM8692/ADM8693/ADM8694/ADM8695
FEATURES
Upgrade for ADM690 to ADM695, MAX690 to MAX695
Specified over temperature
Low power consumption (0.7 mW)
Precision voltage monitor
Reset assertion down to 1 V VCC
Low switch on resistance 0.7 Ω normal, 7 Ω in backup
High current drive (100 mA)
Watchdog timer: 100 ms, 1.6 s, or adjustable
400 nA standby current
Automatic battery backup power switching
Extremely fast gating of chip enable signals (3 ns)
Voltage monitor for power fail
Available in TSSOP package
APPLICATIONS
Microprocessor systems
Computers
Controllers
Intelligent instruments
Automotive systems
PRODUCT HIGHLIGHTS
The ADM8690, ADM8692, and ADM8694 are available in
8-lead, PDIP packages and provide:
1. Power-on reset output during power-up, power-down, and
brownout conditions. The RESET output remains
operational with VCC as low as 1 V.
2. Battery backup switching for CMOS RAM, CMOS
microprocessor, or other low power logic.
3. A reset pulse if the optional watchdog timer has not been
toggled within a specified time.
4. A 1.3 V threshold detector for power-fail warning, low battery
detection, or to monitor a power supply other than 5 V.
The ADM8691, ADM8693, and ADM8695 are available in 16-lead
PDIP and small outline packages (including TSSOP) and
provide three additional functions:
1. Write protection of CMOS RAM or EEPROM.
2. Adjustable reset and watchdog timeout periods.
3. Separate watchdog timeout, backup battery switchover, and
low VCC status outputs.
FUNCTIONAL BLOCK DIAGRAMS
VBATT
VCC
4.65V1
RESET
GENERATOR2
VOUT
RESET
WATCHDOG
INPUT (WDI)
POWER FAIL
INPUT (PFI)
WATCHDOG
TRANSITION DETECTOR
(1.6s)
ADM8690/
ADM8692/
ADM8694
1.3V
POWER FAIL
OUTPUT (PFO)
1VOLTAGE DETECTOR = 4.65V (ADM8690, ADM8694)
4.40V (ADM8692)
2RESET PULSE WIDTH = 50ms (AD8690, ADM8692)
200ms (ADM8694)
Figure 1. ADM8690/ADM8692/ADM8694
VBATT
BATT ON
ADM8691/
ADM8693/
ADM8695
VOUT
VCC
CEIN
4.65V1
OSC IN
OSC SEL
RESET AND
WATCHDOG
TIME BASE
RESET
GENERATOR
CEOUT
LOW LINE
RESET
RESET
WATCHDOG
INPUT (WDI)
POWER FAIL
INPUT (PFI)
WATCHDOG
TRANSITION DETECTOR
1.3V
WATCHDOG
TIMER
WATCHDOG
OUTPUT (WDO)
POWER FAIL
OUTPUT (PFO)
1VOLTAGE DETECTOR = 4.65V (ADM8691, ADM8695)
4.40V (ADM8693)
Figure 2. ADM8691/ADM8693/ADM8695
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
1 page  
ADM8690/ADM8691/ADM8692/ADM8693/ADM8694/ADM8695
Parameter
POWER-FAIL DETECTOR
PFI Input Threshold
PFI Input Current
PFO Output Voltage
PFO Short-Circuit Source Current
PFO Short-Circuit Sink Current
CHIP ENABLE GATING
CEIN Threshold
CEIN Pull-Up Current
CEOUT Output Voltage
CE Propagation Delay
OSCILLATOR
OSC IN Input Current
OSC SEL Input Pull-Up Current
OSC IN Frequency Range
OSC IN Frequency with External Capacitor
Min Typ
1.25 1.3
−25 ±0.01
3.5
13
25
3.0
3
VOUT − 1.5
VOUT − 0.05
3
±2
5
0
4
Max Unit
1.35 V
+25 nA
0.4 V
V
25 μA
mA
0.8 V
V
μA
0.4 V
V
V
7 ns
μA
μA
500 kHz
kHz
1 WDI is a three-level input that is internally biased to 38% of VCC and has an input impedance of approximately 5 MΩ.
Test Conditions/Comments
VCC = 5 V
ISINK = 3.2 mA
ISOURCE = 1 μA
PFI = low, PFO = 0 V
PFI = high, PFO = VOUT
VIL
VIH
ISINK = 3.2 mA
ISOURCE = 3.0 mA
ISOURCE = 1 μA, VCC = 0 V
OSC SEL = 0 V
OSC SEL = 0 V, COSC = 47 pF
Rev. A | Page 5 of 20
5 Page 
ADM8690/ADM8691/ADM8692/ADM8693/ADM8694/ADM8695
In addition to RESET, the ADM8691/ADM8693/ADM8695
contain an active high RESET output. This is the complement of
RESET and is intended for processors requiring an active high
reset signal.
WATCHDOG TIMER RESET
The watchdog timer circuit monitors the activity of the micro-
processor to check that it is not stalled in an indefinite loop. An
output line on the processor is used to toggle the watchdog input
(WDI) line. If this line is not toggled within the selected timeout
period, a RESET pulse is generated. The nominal watchdog
timeout period is preset at 1.6 seconds on the ADM8690/
ADM8692/ADM8694. The ADM8691/ADM8693/ADM8695
can be configured for either a fixed short 100 ms, or a long
1.6 second timeout period, or for an adjustable timeout period. If
the short period is selected, some systems are unable to service
the watchdog timer immediately after a reset, so the ADM8691/
ADM8693/ADM8695 automatically select the long timeout
period directly after a reset is issued. The watchdog timer is
restarted at the end of reset, whether the reset was caused by
lack of activity on WDI or by VCC falling below the reset
threshold.
The normal (short) timeout period becomes effective following
the first transition of WDI after RESET has gone inactive. The
watchdog timeout period restarts with each transition on the
WDI pin. To ensure that the watchdog timer does not time out,
either a high-to-low or low-to-high transition on the WDI pin
must occur at, or less than, the minimum timeout period. If
WDI remains permanently either high or low, reset pulses are
issued after each long (1.6 s) timeout period. The watchdog
monitor can be deactivated by floating the watchdog input
(WDI) or by connecting it to midsupply.
WDI
WDO
RESET
t1
t2 t3
t1
t1
t1 = RESET TIME
t2 = NORMAL (SHORT) WATCHDOG TIMEOUT PERIOD
t3 = WATCHDOG TIMEOUT PERIOD IMMEDIATELY FOLLOWING A RESET
Figure 16. Watchdog Timeout Period and Reset Active Time
Table 5. ADM8691, ADM8693, ADM8695 Reset Pulse Width and Watchdog Timeout Selections
Watchdog Timeout Period
Reset Active Period
OSC SEL
OSC IN
Normal
Immediately After Reset ADM8691/ADM8693 ADM8695
Low 1
External clock input 1024 CLKs
4096 CLKs
512 CLKs
2048 CLKs
Low1
External capacitor 400 ms × C/47 pF 1.6 s × C/47 pF
200 ms × C/47 pF
520 ms × C/47 pF
Floating or high Low
100 ms
1.6 s
50 ms
200 ms
Floating or high Floating or high
1.6 s
1.6 s
50 ms
200 ms
1 With the OSC SEL pin low, OSC IN can be driven by an external clock signal, or an external capacitor (C) can be connected between OSC IN and GND. The nominal
internal oscillator frequency is 10.24 kHz. The nominal oscillator frequency with external capacitor is: FOSC (Hz) = 184,000/C (pF).
Rev. A | Page 11 of 20
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet ADM8694.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| ADM8690 | Microprocessor Supervisory Circuits | Analog Devices |
| ADM8691 | Microprocessor Supervisory Circuits | Analog Devices |
| ADM8692 | Microprocessor Supervisory Circuits | Analog Devices |
| ADM8693 | Microprocessor Supervisory Circuits | Analog Devices |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |