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PDF ADM800L Data sheet ( Hoja de datos )
| Número de pieza | ADM800L | |
| Descripción | Microprocessor Supervisory Circuits | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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a
Microprocessor
Supervisory Circuits
ADM691A/ADM693A/ADM800L/M
FEATURES
Low Power Consumption:
Precision Voltage Monitor
؎2% Tolerance on ADM800L/M
Reset Time Delay—200 ms, or Adjustable
1 A Standby Current
Automatic Battery Backup Power Switching
Fast Onboard Gating of Chip Enable Signals
Also Available in TSSOP Package (ADM691A)
APPLICATIONS
Microprocessor Systems
Computers
Controllers
Intelligent Instruments
Automotive Systems
Critical P Power Monitoring
GENERAL DESCRIPTION
The ADM691A/ADM693A/ADM800L/ADM800M family of
supervisory circuits offers complete single chip solutions for
power supply monitoring and battery control functions in
microprocessor systems. These functions include µP reset,
backup-battery switchover, watchdog timer, CMOS RAM write
protection, and power-failure warning. The family of products
provides an upgrade for the MAX691A/93A/800M family of
products.
All parts are available in 16-pin DIP and SO packages. The
ADM691A is also available in a space-saving TSSOP package.
The following functionality is provided:
1. Power-on reset output during power-up, power-down and
brownout conditions. The circuitry remains operational with
VCC as low as 1 V.
2. Battery backup switching for CMOS RAM, CMOS micro-
processor or other low power logic.
3. A reset pulse if the optional watchdog timer has not been
toggled within a specified time.
4. A 1.25 V threshold detector for power fail warning, low bat-
tery detection, or to monitor a power supply other than +5 V.
FUNCTIONAL BLOCK DIAGRAM
BATT ON
4.65V1
VCC
VBATT
CEIN
CHIP ENABLE
OUTPUT
CONTROL
LOW LINE
VOUT
CEOUT
OSC IN
OSC SEL
RESET &
WATCHDOG
TIMEBASE
RESET &
GENERATOR
WATCHDOG
INPUT (WDI)
POWER FAIL
INPUT (PFI)
WATCHDOG
TRANSITION DETECTOR
WATCHDOG
TIMER
1.25V
ADM691A/ADM693A
ADM800L/ADM800M
RESET
RESET
WATCHDOG
OUTPUT (WDO)
POWER FAIL
OUTPUT (PFO)
1VOLTAGE DETECTOR = 4.4V (ADM693A/ADM800M)
INPUT
POWER
R1
R2
7805 +5V
0.1µF
VCC
CMOS
RAM
BATTERY
NC
VCC
VBATT
BAT VOUT
ON CEOUT
ADM691A CEIN
ADM693A
PFI
GND
ADM800L
ADM800M
WDI
OSC IN
PFO
OSC SEL
RESET
ADDRESS
DECODE
A0–A15 µP
POWER
I/O LINE
NMI µP
RESET
LOW LINE WDO
SYSTEM
STATUS
INDICATORS
Figure 1. Typical Application
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
© Analog Devices, Inc., 1996
1 page  
Typical Performance Curves–ADM691A/ADM693A/ADM800L/M
100
90
80
70
60
50
40
30
20
–50
–25
0 25 50 75
TEMPERATURE – °C
100 125
1.2
1.1
1.0
0.9
0.8
0.7
0.6
–50
–30
–10 10
30 50
TEMPERATURE – °C
70 90
Figure 2. ICC vs. Temperature: Normal Operation
Figure 5. VCC to VOUT ON-Resistance vs. Temperature
60
55
50
45
40
35
30
–50 –30 –10
10
30
50
70
90
TEMPERATURE – °C
Figure 3. IBATT vs. Temperature: Battery Backup Mode
80
70
60
50
40
30
20
–50
–25
0 25 50 75
TEMPERATURE – °C
100 125
Figure 4. Chip Enable ON-Resistance vs. Temperature
80
70
60
50
40
30
20
10
0
40
ROUT = 0.67Ω
60 80 100
IOUT – mA
120
Figure 6. VCC to VOUT Voltage Drop vs. Current
70
60
ROUT = 7Ω
50
40
30
20
10
0
4 6 8 10
IOUT – mA
Figure 7. VBATT to VOUT Voltage Drop vs. Current
REV. 0
–5–
5 Page 
ADM691A/ADM693A/ADM800L/M
RAM Write Protection
The CEOUT line drives the Chip Select inputs of the CMOS
RAM. CEOUT follows CEIN as long as VCC is above the reset
threshold. If VCC falls below the reset threshold, CEOUT goes
high, independent of the logic level at CEIN. This prevents the
microprocessor from writing erroneous data into RAM during
power-up, power-down, brownouts and momentary power in-
terruptions. The LOW LINE output goes low when VCC falls
below the reset threshold.
Watchdog Timer
The microprocessor drives the WATCHDOG INPUT (WDI)
with an I/O line. When OSC IN and OSC SEL are uncon-
nected, the microprocessor must toggle the WDI pin once every
1.6 seconds to verify proper software execution. If a hardware or
software failure occurs such that WDI not toggled a 200 ms
RESET pulse will be generated after 1.6 seconds. This typi-
cally restarts the microprocessor’s power-up routine. A new
RESET pulse is issued every 1.6 seconds until WDI is again
strobed.
The WATCHDOG OUTPUT (WDO) goes low if the watch-
dog timer is not serviced within its timeout period. Once WDO
goes low it remains low until a transition occurs at WDI. The
watchdog timer feature can be disabled by leaving WDI uncon-
nected. OSC IN and OSC SEL also allow other watchdog tim-
ing options.
RESET also goes low if the Watchdog Timer is enabled and
WDI remains either high or low for longer than the watchdog
timeout period.
The RESET output has an internal 1.6 mA pullup, and can ei-
ther connect to an open collector RESET bus or directly drive a
CMOS gate without an external pullup resistor.
INPUT POWER
+5V
0.1µF
3V
BATTERY
R1
R2
NC
VCC
VBATT
BATT VOUT
ON CEOUT
ADM691A
ADM693A CEIN
ADM800L
PFI ADM800M
GND
OSC IN
OSC SEL
WDI
PFO
RESET
LOW LINE WDO
0.1µF
CMOS
RAM
ADDRESS
DECODE
RESET
A0–A15
I/O LINE
NMI µP
RESET
0.1µF
SYSTEM STATUS
INDICATORS
Figure 24. Typical Application Circuit
REV. 0
–11–
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