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PDF ADM706P Data sheet ( Hoja de datos )
| Número de pieza | ADM706P | |
| Descripción | +3 V/ Voltage Monitoring uP Supervisory Circuits | |
| Fabricantes | Analog Devices | |
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a
+3 V, Voltage Monitoring
P Supervisory Circuits
ADM706P/R/S/T, ADM708R/S/T
FEATURES
Precision Supply-Voltage Monitor
+2.63 V (ADM706P/R, ADM708R)
+2.93 V (ADM706S, ADM708S)
+3.08 V (ADM706T, ADM708T)
100 A Quiescent Current
200 ms Reset Pulsewidth
Debounced Manual Reset Input (MR)
Independent Watchdog Timer—1.6 sec Timeout
(ADM706x)
Reset Output
Active High (ADM706P)
Active Low (ADM706R/S/T)
Both Active High and Active Low (ADM708R/S/T)
Voltage Monitor for Power-Fail or Low Battery Warning
Guaranteed RESET Valid with VCC = 1 V
Superior Upgrade for MAX706P/R/S/T, MAX708R/S/T
APPLICATIONS
Microprocessor Systems
Computers
Controllers
Intelligent Instruments
Critical P Monitoring
Automotive Systems
Battery Operated Systems
Portable Instruments
GENERAL DESCRIPTION
The ADM706P/R/S/T and the ADM708R/S/T microprocessor
supervisory circuits are suitable for monitoring either 3 V or 3.3 V
power supplies.
The ADM706P/R/S/T provide the following functions:
1. Power-supply monitoring circuitry which generates a Reset
output during power-up, power-down and brownout condi-
tions. The reset output remains operational with VCC as low
as 1 V.
2. Independent watchdog monitoring circuitry which is acti-
vated if the watchdog input has not been toggled within
1.6 seconds.
3. A 1.25 V threshold detector for power fail warning, low bat-
tery detection, or to monitor an additional power supply.
4. An active low debounced manual reset input (MR).
The ADM706R, ADM706S, ADM706T are identical except for
the reset threshold monitor levels which are 2.63 V, 2.93 V, and
3.08 V respectively. The ADM706P is identical to the ADM706R
in that the reset threshold is 2.63 V. It differs only in that it has
an active high reset output.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
FUNCTIONAL BLOCK DIAGRAMS
WATCHDOG
INPUT (WDI)
WATCHDOG
TRANSITION
DETECTOR
WATCHDOG
TIMER
WATCHDOG
OUTPUT(WDO)
VCC
70A
MR
VCC
VREF*
POWER FAIL
INPUT (PFI)
1.25V
RESET &
WATCHDOG
TIMEBASE
RESET
GENERATOR
RESET,
(P = RESET)
ADM706
POWER FAIL
OUTPUT (PFO)
*VOLTAGE REFERENCE = 2.63V (P/R), 2.93V (S), 3.08V (T)
VCC
70A
MR
RESET
GENERATOR
RESET
RESET
VCC
VREF*
POWER FAIL
INPUT (PFI)
1.25V
ADM708
POWER FAIL
OUTPUT (PFO)
*VOLTAGE REFERENCE = 2.63V (R), 2.93V (S), 3.08V (T)
The ADM708R/S/T provide the same functionality as the
ADM706R/S/T and only differ in that:
1. A watchdog timer function is not available.
2. An active high reset output (RESET) in addition to the
active low (RESET) output is available.
All parts are available in 8-lead DIP and narrow SOIC packages.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
1 page  
ADM706P/R/S/T, ADM708R/S/T
WATCHDOG
INPUT (WDI)
WATCHDOG
TRANSITION
DETECTOR
WATCHDOG
TIMER
WATCHDOG
OUTPUT(WDO)
VCC
70A
MR
VCC
VREF*
POWER FAIL
INPUT (PFI)
1.25V
RESET &
WATCHDOG
TIMEBASE
RESET
GENERATOR
RESET,
(P = RESET)
ADM706
POWER FAIL
OUTPUT (PFO)
*VOLTAGE REFERENCE = 2.63V (P/R), 2.93V (S), 3.08V (T)
Figure 1. ADM706 Functional Block Diagram
VCC
70A
MR
RESET
GENERATOR
RESET
RESET
VCC
VREF*
POWER FAIL
INPUT (PFI)
1.25V
ADM708
POWER FAIL
OUTPUT (PFO)
*VOLTAGE REFERENCE = 2.63V (R), 2.93V (S), 3.08V (T)
Figure 2. ADM708 Functional Block Diagram
CIRCUIT INFORMATION
Power Fail Reset
The reset output provides a reset (RESET or RESET) output
signal to the Microprocessor whenever the VCC input is below
the reset threshold. The actual reset threshold voltage is depen-
dent on whether a P/R, S, or T suffix device is used. An internal
timer holds the reset output active for 200 ms after the voltage
on VCC rises above the threshold. This is intended as a power-on
reset signal for the microprocessor. It allows time for both the
power supply and the microprocessor to stabilize after power-
up. If a power supply brownout or interruption occurs, the reset
line is similarly activated and remains active for 200 ms after the
supply recovers. If another interruption occurs during an active
reset period, then the reset timeout period continues for an ad-
ditional 200 ms.
The reset output is guaranteed to remain valid with VCC as low
as 1 V. This ensures that the microprocessor is held in a stable
shutdown condition as the power supply starts up.
The ADM706P provides an active high reset (RESET) signal;
the ADM706R/S/T provides an active low (RESET) signal;
while the ADM708R/S/T provides both RESET and RESET.
Manual Reset
The manual reset input (MR) allows other reset sources such as
a manual reset switch to generate a processor reset. The input is
effectively debounced by the timeout period (200 ms typical).
The MR input is TTL/CMOS compatible so it may also be
driven by any logic reset output. If unused, the MR input may
be tied high or left floating.
VCC
RESET
VRT
VRT
tRS
tRS
MR MR EXTERNALLY
DRIVEN LOW
WDO
NOTE: RESET = COMPLEMENT OF RESET
Figure 3. RESET, MR and WDO Timing
Watchdog Timer (ADM706)
The watchdog timer circuit may be used to monitor the activity
of the microprocessor in order to check that it is not stalled in
an indefinite loop. An output line on the processor is used to
toggle the Watchdog Input (WDI) line. If this line is not toggled
within the timeout period (1.6 sec), the watchdog output
(WDO) is driven low. The WDO output may be connected to a
nonmaskable interrupt (NMI) on the processor. Therefore, if
the watchdog timer times out, an interrupt is generated. The in-
terrupt service routine should then be used to rectify the
problem.
The watchdog timer is cleared by either a high-to-low or by a
low-to-high transition on WDI. Pulses as narrow as 50 ns are
detected. The timer is also cleared by RESET/RESET going
active. Therefore the watchdog timeout period begins after reset
goes inactive.
When VCC falls below the reset threshold, WDO is forced low
whether or not the watchdog timer has timed out. Normally
this would generate an interrupt but it is overridden by RESET/
RESET going active.
The watchdog monitor can be deactivated by floating the
Watchdog Input (WDI). The WDO output can now be used as
a low line output since it will only go low when VCC falls below
the reset threshold.
tWP
WDI
tWD
tWD tWD
WDO
RESET
RESET EXTERNALLY
TRIGGERED BY MR
Figure 4. Watchdog Timing
tRS
REV. A
–5–
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| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet ADM706P.PDF ] | |
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