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PDF ADM705 Data sheet ( Hoja de datos )

Número de pieza ADM705
Descripción Low Cost uP Supervisory Circuits
Fabricantes Analog Devices 
Logotipo Analog Devices Logotipo



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a
FEATURES
Guaranteed RESET Valid with VCC = 1 V
190 A Quiescent Current
Precision Supply-Voltage Monitor
4.65 V (ADM705/ADM707)
4.40 V (ADM706/ADM708)
200 ms Reset Pulsewidth
Debounced TTL/CMOS Manual Reset Input (MR)
Independent Watchdog Timer—1.6 sec Timeout
(ADM705/ADM706)
Active High Reset Output (ADM707/ADM708)
Voltage Monitor for Power-Fail or Low Battery
Warning
Superior Upgrade for MAX705–MAX708
Also Available in MicroSOIC Packages
APPLICATIONS
Microprocessor Systems
Computers
Controllers
Intelligent Instruments
Critical P Monitoring
Automotive Systems
Critical P Power Monitoring
GENERAL DESCRIPTION
The ADM705–ADM708 are low cost µP supervisory circuits.
They are suitable for monitoring the 5 V power supply/battery
and can also monitor microprocessor activity.
The ADM705/ADM706 provide the following functions:
1. Power-On Reset output during power-up, power-down and
brownout conditions. The RESET output remains opera-
tional with VCC as low as 1 V.
2. Independent watchdog timeout, WDO, that goes low if the
watchdog input has not been toggled within 1.6 seconds.
3. A 1.25 V threshold detector for power-fail warning, low
battery detection or to monitor a power supply other than
5 V.
4. An active low debounced manual reset input (MR).
The ADM707/ADM708 differ in that:
1. A watchdog timer function is not available.
2. An active high reset output in addition to the active low
output is available.
Low Cost P
Supervisory Circuits
ADM705–ADM708
FUNCTIONAL BLOCK DIAGRAMS
WATCHDOG
INPUT (WDI)
WATCHDOG
TRANSITION
DETECTOR
WATCHDOG
TIMER
WATCHDOG
OUTPUT (WDO)
VCC
250A
MR
VCC
POWER-FAIL
INPUT (PFI)
4.65V*
1.25V
RESET &
WATCHDOG
TIMEBASE
RESET
GENERATOR
ADM705/
ADM706
RESET
POWER-FAIL
OUTPUT (PFO)
*VOLTAGE REFERENCE = 4.65V (ADM705), 4.40V (ADM706)
VCC
250A
MR
VCC
POWER-FAIL
INPUT (PFI)
4.65V*
1.25V
RESET
GENERATOR
ADM707/
ADM708
RESET
RESET
POWER-FAIL
OUTPUT (PFO)
*VOLTAGE REFERENCE = 4.65V (ADM707), 4.40V (ADM708)
Two supply-voltage monitor levels are available. The ADM705/
ADM707 generate a reset when the supply voltage falls below
4.65 V, while the ADM706/ADM708 require that the supply
fall below 4.40 V before a reset is issued.
All parts are available in 8-lead DIP and SOIC packages. The
ADM707 and ADM708 are also available in space-saving
microSOIC packages.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000

1 page




ADM705 pdf
ADM705–ADM708
Power-Fail Comparator
The power-fail comparator is an independent comparator that
may be used to monitor the input power supply. The comparator’s
inverting input is internally connected to a 1.25 V reference
voltage. The noninverting input is available at the PFI input.
This input may be used to monitor the input power supply via
a resistive divider network. When the voltage on the PFI input
drops below 1.25 V, the comparator output (PFO) goes low,
indicating a power failure. For early warning of power failure,
the comparator may be used to monitor the preregulator input
simply by choosing an appropriate resistive divider network.
The PFO output can be used to interrupt the processor so that
a shutdown procedure is implemented before the power is lost.
INPUT
POWER
R1
1.25V
PFO
POWER-FAIL PFI
R2
INPUT
ADM70x
POWER-FAIL
OUTPUT
Figure 5. Power-Fail Comparator
Adding Hysteresis to the Power-Fail Comparator
For increased noise immunity, hysteresis may be added to the
power-fail comparator. Since the comparator circuit is non-
inverting, hysteresis can be added simply by connecting a
resistor between the PFO output and the PFI input as shown in
Figure 6. When PFO is low, resistor R3 sinks current from the
summing junction at the PFI pin. When PFO is high, resistor
R3 sources current into the PFI summing junction. This results
in differing trip levels for the comparator. Further noise immu-
nity may be achieved by connecting a capacitor between PFI
and GND.
7V TO 15V
INPUT POWER
R1
R2
ADM663
5V
VCC
1.25V
PFO
PFI
ADM70x
R3
TO P NMI
[VH
= 1.25
1
+

R2
R2
+
×
R3
R3
R1]
VL
=
1.25
+
R1

1.25
R2
VCC
1.25
RE

VMID
=
1.25

R1 + R2
R2 
Valid RESET Below 1 V VCC
The ADM70x family of products is guaranteed to provide a
valid reset level with VCC as low as 1 V; please refer to the Typi-
cal Performance Characteristics. As VCC drops below 1 V, the
internal transistor will not have sufficient drive to hold it ON so
the voltage on RESET will no longer be held at 0 V. A pull-down
resistor as shown in Figure 7 may be connected externally to
hold the line low if it is required.
ADM70x
RESET
GND
R1
Figure 7. RESET Valid Below 1 V
5V
PFO
0V
0V
VL VH
VIN
Figure 6. Adding Hysteresis to the Power-Fail Comparator
REV. B
–5–

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