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PDF ADV7175 Data sheet ( Hoja de datos )
| Número de pieza | ADV7175 | |
| Descripción | Integrated Digital CCIR-601 YCrCb to PAL/NTSC Video Encoder | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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a
Integrated Digital CCIR-601
YCrCb to PAL/NTSC Video Encoder
ADV7175/ADV7176
FEATURES
Close Captioning Support
CCIR-601 YCrCb to PAL/NTSC Video Encoder
Teletext Support (Passthrough Mode)
Single 27 MHz Clock Required (؋2 Oversampling)
On-Board Color Bar Generation
Pixel Port Supports:
CCIR-656 4:2:2 8-Bit Parallel Input Format
On-Board Voltage Reference
2-Wire Serial MPU Interface (I2C Compatible)
4:2:2 16-Bit Parallel Input Format
+5 V CMOS Monolithic Construction
SMPTE 170M NTSC Compatible Composite Video Output
44-Pin PQFP Thermally Enhanced Package
CCIR624/CCIR601 PAL Compatible Composite Video Output
SCART/PeriTV Support
YUV Output Mode
Simultaneous Composite and S-VHS Y/C or RGB YUV
Video Outputs
Programmable Luma Filters (Low-Pass/Notch)
Square Pixel Support (Slave Mode)
Allows Subcarrier Phase Locking with External Video
Source
APPLICATIONS
MPEG-1 and MPEG-2 Video
DVD
Digital Satellite/Cable Systems (Set Top Boxes/IRDs)
Video Games
CD Video/Karaoke
Professional Studio Quality
PC Video/Multimedia
10-Bit DAC Resolution for Encoded Video Channels
8-Bit DAC Resolution for RGB Output
YUV Interpolation for Accurate Subcarrier Construction
Programmable Subcarrier Frequency and Phase
Programmable LUMA Delay
Color Signal Control/Burst Signal Control
Interlaced/Noninterlaced Operation
Complete On-Chip Video Timing Generator
Master/Slave Operation Supported
Master Mode Timing Programmability
Macrovision Antitaping Facility Rev 6.1/7.x (ADV7175 Only)*
GENERAL DESCRIPTION
The ADV7175/ADV7176 is an integrated digital video encoder
that converts Digital CCIR-601 4:2:2 component video data into a
standard analog baseband television signal compatible with world
wide standards NTSC, PAL B/D/G/H/I, PAL M or PAL N. In
addition to the composite output signal, there is the facility to out-
put S-VHS Y/C video, YUV or RGB video. The Y/C, YUV or
RGB format is simultaneously available at the analog outputs with
the composite video signal. Each analog output generates a
standard video-level signal into a doubly terminated 75 Ω load.
(Continued on page 6)
FUNCTIONAL BLOCK DIAGRAM
VAA
RESET
COLOR
DATA
P7–P0
P15–P8
8
4:2:2 TO
4:4:4
INTER-
POLATOR
8
8
YCrCb
TO
YUV
MATRIX
HSYNC
FIELD/VSYNC
BLANK
VIDEO TIMING
GENERATOR
YUV TO
RBG
MATRIX
8
8
8
8
ADD 8
INTER-
8
Y 10
LOW-PASS
SYNC
POLATOR
FILTER
8
ADD 8
BURST
INTER- 8
POLATOR
U 10
LOW-PASS
FILTER
8 ADD 8
BURST
I2C MPU PORT
INTER- 8
POLATOR
V
LOW-PASS
FILTER
REAL-TIME
CONTROL
CIRCUIT
10
10 10
SIN/COS
DDS BLOCK
M
U 10
L
T
I
P
10
L
E
X 10
E
R
10-BIT
DAC
10-BIT
DAC
10-BIT
DAC
10 10-BIT
DAC
ADV7175/ADV7176
VOLTAGE
REFERENCE
CIRCUIT
GREEN/
LUMA/
Y
RED/
CHROMA/
V
BLUE/
COMPOSITE/
U
COMPOSITE
VREF
RSET
COMP
CLOCK
SCLOCK SDATA ALSB
SCRESET/RTC
GND
*This device is protected by U.S. Patent Numbers 4631603, 4577216, 4819098 a nd other intellectual property rights. The Macrovision anticopy process is
licensed for noncommercial home use only, which is its sole intended use in the devic e. Please contact sales office for latest Macrovision version available.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1996
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
1 page  
Mnemonic
P15-P0
CLOCK
HSYNC
FIELD/VSYNC
BLANK
SCRESET/RTC
VREF
RSET
COMP
COMPOSITE
RED/CHROMA/V
GREEN/LUMA/Y
BLUE/COMPOSITE/U
SCLOCK
SDATA
ALSB
RESET
VAA
GND
ADV7175/ADV7176
PIN DESCRIPTION
Input/Output Function
I 8-Bit 4:2:2 Multiplexed YCrCb Pixel Port (P7–P0) or
16-Bit YCrCb Pixel Port (P15–P0). P0 represents the LSB.
I TTL Clock Input. Requires a stable 27 MHz reference Clock for proper operation.
Alternatively a 24.52 MHz (NTSC) or 29.5 MHz (PAL) can be used for square pixel
operation.
I/O HSYNC (Modes 1 & 2) Control Signal. This pin may be configured to output (Mas-
ter Mode) or accept (Slave Mode) Sync signals.
I/O Dual Function FIELD (Mode 1) and VSYNC (Mode 2) Control Signal. This pin may
be configured to output (Master Mode) or accept (Slave Mode) these control signals.
I/O Video Blanking Control Signal. The pixel inputs are ignored when this is logic level
“0.” This signal is optional.
I This pin can be configured as an input by setting MR22 and MR21 of Mode
Register 2. It can be configured as a subcarrier reset pin, in which case a high to low
transition on this pin will reset the subcarrier to field 0. Alternatively it may be con-
figured as a Real Time Control (RTC) input.
I/O Voltage Reference Input for DACs or Voltage Reference Output (1.2 V).
I A 150 Ω resistor connected from this pin to GND is used to control full-scale ampli-
tudes of the video signals.
O Compensation Pin. Connect a 0.1 µF capacitor from COMP to VAA.
O PAL/NTSC Composite Video Output. Full-Scale Output is 180IRE (1286 mV) for
NTSC and 1300 mV for PAL.
O RED/S-VHS C/V Analog Output.
O GREEN/S-VHS Y/Y Analog Output.
O BLUE/Composite/U Analog Output.
I MPU Port Serial Interface Clock Input.
I/O MPU Port Serial Data Input/Output.
I TTL Address Input. This signal set up the LSB of the MPU address.
I The input resets the on chip timing generator and sets the ADV7175/ADV7176 into
default mode. This is NTSC operation, Timing Slave Mode 0, 8-bit operation, 2 ×
composite & S VHS out.
P +5 V Supply.
G Ground Pin.
PIN CONFIGURATION
44 43 42 41 40 39 38 37 36 35 34
VAA 1
P5 2
P6 3
P7 4
P8 5
P9 6
P10 7
P11 8
P12 9
GND 10
VAA 11
PIN 1
IDENTIFIER
ADV7175/ADV7176
PQFP
TOP VIEW
(Not to Scale)
33 VREF
32 COMPOSITE
31 BLUE/COMPOSITE/U
30 VAA
29 GND
28 VAA
27 GREEN/LUMA/Y
26 RED/CHROMA/V
25 COMP
24 SDATA
23 SCLOCK
12 13 14 15 16 17 18 19 20 21 22
REV. A
–5–
5 Page 
ADV7175/ADV7176
Mode 1: Slave Option. HSYNC, BLANK, FIELD.
(Timing Register 0 TR0 = X X X X X 0 1 0)
In this mode the ADV7175/ADV7176 accepts horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD input
when HSYNC is low indicates a new frame, i.e., vertical retrace. The BLANK signal is optional. When the BLANK input is disabled
the ADV7175/ADV7176 automatically blanks all normally blank lines as per CCIR-624. Mode 1 is illustrated in Figure 17 (NTSC)
and Figure 18 (PAL).
DISPLAY
VERTICAL BLANK
DISPLAY
522 523 524 525
1
2
3
4
5
6
7
8
9 10 11
HSYNC
BLANK
FIELD
EVEN FIELD ODD FIELD
DISPLAY
VERTICAL BLANK
20 21 22
DISPLAY
260 261 262 263 264 265 266 267 268 269 270 271 272 273 274
HSYNC
BLANK
FIELD
ODD FIELD EVEN FIELD
Figure 17. Timing Mode 1 (NTSC)
DISPLAY
VERTICAL BLANK
283 284 285
DISPLAY
622 623 624 625
1
2
3
4
5
6
7
HSYNC
BLANK
FIELD
EVEN FIELD ODD FIELD
DISPLAY
VERTICAL BLANK
21 22 23
DISPLAY
309 310 311 312 313 314 315 316 317 318 319 320
HSYNC
BLANK
FIELD
ODD FIELD EVEN FIELD
Figure 18. Timing Mode 1 (PAL)
REV. A
–11–
334 335 336
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ADV7175.PDF ] | |
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