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PDF ADuM1100 Data sheet ( Hoja de datos )
| Número de pieza | ADuM1100 | |
| Descripción | iCoupler Digital Isolator | |
| Fabricantes | Analog Devices | |
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a
iCoupler® Digital Isolator
ADuM1100
FEATURES
High Data Rate: DC to 100 Mbps (NRZ)
Compatible with 3.3 V and 5.0 V Operation/
Level Translation
125؇C Max Operating Temperature
Low Power Operation
5 V Operation
1.0 mA Max @ 1 Mbps
4.5 mA Max @ 25 Mbps
16.8 mA Max @ 100 Mbps
3.3 V Operation
0.4 mA Max @ 1 Mbps
3.5 mA Max @ 25 Mbps
7.1 mA Max @ 50 Mbps
8-Lead SOIC Package (lead-free version available)
High Common-Mode Transient Immunity: >25 kV/s
Safety and Regulatory Information
UL Recognized
2500 V rms for 1 Minute per UL 1577
CSA Component Acceptance Notice No. 5A
VDE Certificate of Conformity
DIN EN 60747-5-2 (VDE 0884 Part 2): 2003–01
DIN EN 60950 (VDE 0805): 2001–12; EN 60950: 2000
VIORM = 560 VPEAK
GENERAL DESCRIPTION
The ADuM1100 is a digital isolator based on Analog Devices’
iCoupler technology. Combining high speed CMOS and mono-
lithic air core transformer technology, this isolation component
provides outstanding performance characteristics superior to
alternatives such as optocoupler devices.
Configured as a pin compatible replacement for existing high speed
optocouplers, the ADuM1100 supports data rates as high as
25 Mbps and 100 Mbps.
The ADuM1100 operates with either voltage supply ranging from
3.0 V to 5.5 V, boasts a propagation delay of <18 ns and edge
asymmetry of <2 ns, and is compatible with temperatures up to
125°C. It operates at very low power, less than 0.9 mA of quiescent
current (sum of both sides), and a dynamic current of less than
160 µA per Mbps of data rate. Unlike other optocoupler alter-
natives, the ADuM1100 provides dc correctness with a patented
refresh feature that continuously updates the output signal.
The ADuM1100 is offered in three grades. The ADuM1100AR
and ADuM1100BR can operate up to a maximum temperature
of 105°C and support data rates up to 25 Mbps and 100 Mbps,
respectively. The ADuM1100UR can operate up to a maximum
temperature of 125°C and supports data rates up to 100 Mbps.
APPLICATIONS
Digital Fieldbus Isolation
Opto-Isolator Replacement
Computer-Peripheral Interface
Microprocessor System Interface
General Instrumentation and Data Acquisition
Applications
FUNCTIONAL BLOCK DIAGRAM
VDD1
VI
(DATA IN)
VDD1
GND1
ED
NE
CC
OO
DD
EE
UPDATE
WATCHDOG
ADuM1100
FOR PRINCIPLES OF OPERATION, SEE METHOD OF OPERATION,
DC CORRECTNESS, AND MAGNETIC FIELD IMMUNITY SECTION.
VDD2
GND2
VO
(DATA OUT)
GND2
REV. E
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.
1 page  
ADuM1100
Parameter
Symbol Min Typ Max Unit Test Conditions
SWITCHING SPECIFICATIONS (continued)
Propagation Delay Skew
(Equal Temperature, Supplies)6, 8
5 V/3 V Operation
3 V/5 V Operation
Output Rise/Fall Time (10% to 90%)
Common-Mode Transient Immunity at
Logic Low/High Output8
Input Dynamic Power Dissipation Capacitance10
5 V/3 V Operation
3 V/5 V Operation
Output Dynamic Power Dissipation Capacitance10
5 V/3 V Operation
3 V/5 V Operation
tPSK2
tR, tf
|CML|,
|CMH|
CPD1
CPD2
25
3
35
35
47
8
14
9
12
ns CL = 15 pF, CMOS Signal Levels
ns CL = 15 pF, CMOS Signal Levels
ns CL = 15 pF, CMOS Signal Levels
kV/µs VI = 0 or VDD1, VCM = 1000 V,
Transient Magnitude = 800 V
pF
pF
pF
pF
NOTES
1All voltages are relative to their respective ground.
2Output supply current values are with no output load present. The supply current drawn at a given signal frequency when an output load is present is given by
IDD2(L) = IDD2 + VDD2 × f × CL, where IDD2 is the unloaded output supply current, f is the input signal frequency, and CL is the output load capacitance.
3The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
4The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
5tPHL is measured from the 50% level of the falling edge of the VI signal to the 50% level of the falling edge of the VO signal. tPLH is measured from the 50% level of
the rising edge of the VI signal to the 50% level of the rising edge of the VO signal.
6Since the input thresholds of the ADuM1100 are at voltages other than the 50% level of typical input signals, the measured propagation delay and pulse width distortion
may be affected by slow input rise/fall times. See the Propagation Delay-Related Parameters section and Figures 3 to 7 for information on the impact of given input
rise/fall times on these parameters.
7Pulse width distortion change versus temperature is the absolute value of the change in pulse width distortion for a 1°C change in operating temperature.
8tPSK1 is the magnitude of the worst-case difference in tPHL and/or tPLH that will be measured between units at the same operating temperature and output load within
the recommended operating conditions. tPSK2 is the magnitude of the worst-case difference in tPHL and/or tPLH that will be measured between units at the same operating
temperature, supply voltages, and output load within the recommended operating conditions.
9CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining V O > 0.8 VDD2. CML is the maximum common-mode voltage slew
rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling edges. The transient magnitude is the
range over which the common-mode is slewed.
10The dynamic power dissipation capacitance is given by
CPDi = (IDDi(100) – IDDi(Q))/(VDDi × f), where i = 1 or 2 and f is the input signal frequency.
The supply current consumptions at a given frequency and output load are calculated as
IDD1 = CPD1 × VDD1 × f + IDD1(Q); IDD2(L) = (CPD2 + CL) × VDD2 × f + IDD2(Q), where CL is the output load capacitance.
Specifications subject to change without notice.
PACKAGE CHARACTERISTICS
Parameter
Symbol Min Typ Max Unit Test Conditions
Resistance (Input-Output)1
Capacitance (Input-Output)1
Input Capacitance2
Input IC Junction-to-Case
Thermal Resistance
Output IC Junction-to-Case
Thermal Resistance
Package Power Dissipation
RI–O
CI–O
CI
θJCI
θJCO
PPD
1012
1
4.0
46
41
240
Ω
pF
pF
°C/W
°C/W
mW
f = 1 MHz
Thermocouple Located at Center
Underside of Package
NOTES
1Device considered a 2-terminal device: Pins 1, 2, 3, and 4 shorted together and Pins 5, 6, 7, and 8 shorted together.
2Input capacitance is measured at Pin 2 (VI).
REV. E
–5–
5 Page 
4
3
5V INPUT SIGNAL
2
1
3.3V INPUT SIGNAL
0
1 2 3 4 5 6 7 8 9 10
INPUT RISE TIME (10%–90%, ns)
Figure 5. Typical Propagation Delay Change due to
Input Rise Time Variation (for VDD1 = 3.3 V and 5 V)
0
–1
5V INPUT SIGNAL
–2
3.3V INPUT SIGNAL
–3
–4
1 2 3 4 5 6 7 8 9 10
INPUT RISE TIME (10%–90%, ns)
Figure 6. Typical Propagation Delay Change due to
Input Fall Time Variation (for VDD1 = 3.3 V and 5 V)
The impact of the slower input edge rates can also affect the
measured pulse width distortion as based on the input 50% level.
This impact may either increase or decrease the apparent pulse
width distortion depending on the relative magnitudes of tPHL,
tPLH, and PWD. The case of interest here is the condition
that leads to the largest increase in pulse width distortion. The
change in this case is given by
∆PWD = PWD′ – PWD = ∆LH – ∆HL =
( )( ) ( )t /0.8V1 V –VITH(L–H) –VITH(H–L) , for t = tr = t f
where:
PWD = tPLH – tPHL
PWD′ = t ′PLH – t ′PHL
This adjustment in pulse width distortion is plotted as a func-
tion of input rise/fall time in Figure 7.
ADuM1100
6
5
4
5V INPUT SIGNAL
3
3.3V INPUT SIGNAL
2
1
0
1 2 3 4 5 6 7 8 9 10
INPUT RISE/FALL TIME (10%–90%, ns)
Figure 7. Typical Pulse Width Distortion Adjustment due
to Input Rise/Fall Time Variation (at VDD1 = 3.3 V and 5 V)
Method of Operation, DC Correctness, and
Magnetic Field Immunity
Referring to the functional block diagram, the two coils act as a
pulse transformer. Positive and negative logic transitions at the
isolator input cause narrow (2 ns) pulses to be sent via the trans-
former to the decoder. The decoder is bistable and therefore
either set or reset by the pulses indicating input logic transitions.
In the absence of logic transitions at the input for more than 2 µs,
a periodic update pulse of the appropriate polarity is sent to ensure
dc correctness at the output. If the decoder receives none of
these update pulses for more than about 5 µs, the input side is
assumed to be unpowered or nonfunctional, in which case the
isolator output is forced to a logic high state by the watchdog
timer circuit.
The limitation on the ADuM1100’s magnetic field immunity is set
by the condition in which induced voltage in the transformer’s
receiving coil is sufficiently large to either falsely set or reset the
decoder. The analysis that follows defines the conditions under
which this may occur. The ADuM1100’s 3.3 V operating condi-
tion is examined because it represents the most susceptible mode
of operation.
The pulses at the transformer output are greater than 1.0 V in
amplitude. The decoder has sensing thresholds at about 0.5 V,
therefore establishing a 0.5 V margin in which induced voltages can
be tolerated. The induced voltage induced across the receiving
coil is given by
V = (– dβ /dt) Σπ rn2; n = 1, 2, . . . . , N
where:
β = magnetic flux density (Gauss).
N = number of turns in receiving coil.
rn = radius of nth turn in receiving coil (cm).
REV. E
–11–
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet ADuM1100.PDF ] | |
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