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PDF ADUC844 Data sheet ( Hoja de datos )
| Número de pieza | ADUC844 | |
| Descripción | MicroConverter/ Dual 16-Bit/24-Bit ADCs with Embedded 62kB FLASH MCU | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ADUC844 (archivo pdf) en la parte inferior de esta página. Total 20 Páginas | ||
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PRELIMINARY TECHNICAL DATA
a
MicroConverter, Dual 16-Bit/24-Bit ADCs
with Embedded 62kB FLASH MCU
Preliminary Technical Data
ADuC844
FEATURES
High Resolution Sigma-Delta ADCs
Two Independent ADCs (24-Bit and 16-Bit Resolution)
24-Bit No Missing Codes, Primary ADC
21-Bit rms (18.5 Bit p-p) Effective Resolution @ 20 Hz
Offset Drift 10 nV/°C, Gain Drift 0.5 ppm/°C
Memory
62 Kbytes On-Chip Flash/EE Program Memory
4 Kbytes On-Chip Flash/EE Data Memory
Flash/EE, 100 Year Retention, 100 Kcycles Endurance
3 Levels of Flash/EE Program Memory Security
In-Circuit Serial Download (No External Hardware)
High Speed User Download (5 Seconds)
2304 Bytes On-Chip Data RAM
8051-Based Core
8051 Compatible Instruction Set
High Performance Single Cycle Core
32 kHz External Crystal
On-Chip Programmable PLL (12.58 MHz Max)
3 × 16-Bit Timer/Counter
26 Programmable I/O Lines
11 Interrupt Sources, Two Priority Levels
Dual Data Pointer, Extended 11-Bit Stack Pointer
On-Chip Peripherals
Internal Power on Reset Circuit
12-Bit Voltage Output DAC
Dual 16-Bit S-D DACs/PWMs
On-Chip Temperature Sensor
Dual Excitation Current Sources
Time Interval Counter (Wakeup/RTC Timer)
UART, SPI®, and I2C® Serial I/O
High Speed Baud Rate Generator (incl 115,200)
Watchdog Timer (WDT)
Power Supply Monitor (PSM)
Power
Normal: 2.3mA Max @ 3.6 V (Core CLK = 1.57 MHz)
Power-Down: 20µA Max with Wakeup Timer Running
Specified for 3 V and 5 V Operation
Package and Temperature Range
52-Lead MQFP (14 mm × 14 mm), –40°C to +125°C
56-Lead CSP (8 mm × 8 mm), –40°C to +85°C
APPLICATIONS
Intelligent Sensors
WeighScales
Portable Instrumentation, Battery Powered Systems
4-20mA Transmitters
Data Logging
Precision System Monitoring
REV. PrB
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
No license is granted by implication or otherwise under any patent or patent rights
of Analog Devices. Trademarks and registered trademarks are the property of their
respective companies.
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The ADuC844 is a complete smart transducer front end, integrating
two high resolution sigma-delta ADCs, an 8-bit MCU, and
program/data Flash/EE memory on a single chip.
The two independent ADCs (primary and auxiliary) include a
temperature sensor and a PGA (allowing direct measurement of low
level signals). The ADCs with on-chip digital filtering and
programmable output data rates are intended for the measurement of
wide dynamic range, low frequency signals, such as those in weigh
scale, strain-gage, pressure transducer, or temperature measurement
applications.
The device operates from a 32 kHz crystal with an on-chip PLL
generating a high frequency clock of 12.58 MHz. This clock is routed
through a programmable clock divider from which the MCU core
clock operating frequency is generated. The microcontroller core is an
optimized single cycle 8052 offering up to 12.58MIPs performance
while maintaining the 8051 instruction set compatibility.
62 Kbytes of nonvolatile Flash/EE program memory, 4 Kbytes of
nonvolatile Flash/EE data memory, and 2304 bytes of data RAM are
provided on-chip. The program memory can be configured as data
memory to give up to 60 Kbytes of NV data memory in data logging
applications.
On-chip factory firmware supports in-circuit serial download and
debug modes (via UART), as well as single-pin emulation mode via
the EA pin. The ADuC844 is supported by a QuickStart™
development system featuring low cost software and hardware
development tools.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© 2003 Analog Devices, Inc. All rights reserved.
1 page  
PRELIMINARY TECHNICAL DATA
ADuC844
PARAMETER
LOGIC INPUTS
All Inputs except SCLOCK, RESET
and XTAL12
VINL, Input Low Voltage
VINH, Input Low Voltage
SCLOCK and RESET Only
(Schmidt Triggered Inputs) 2
VT+
VT-
VT+ - VT-
Input Currents
Port 0, P1.2àP1.7, EA
SCLOCK, MOSI,MISO SS13
RESET
P1.0, P1.1, Port 2, Port 3
Input Capacitance
LOGIC OUTPUTS
All Digital Outputs except XTAL22
VOH, Output High Voltage
VOL, Output Low Voltage14
MIN
2.0
1.3
0.95
0.8
0.4
0.3
2.0
-10
35
-180
-20
2.4
2.4
Floating State Leakage Current
Floating State Output Capacitance
START UP TIME
At Power On
After External RESET in Normal Mode
After WDT RESET in Normal Mode
From Idle Mode
From Power-Down Mode
Oscillator Running
Wakeup with INT0 Interrupt
Wakeup with SPI Interrupt
Wakeup with TIC Interrupt
Wakeup with External RESET
Oscillator Powered Down
Wakeup with INT0 Interrupt
Wakeup with SPI Interrupt
Wakeup with External RESET
TYP
5
5
300
3
3
10
20
20
20
3
20
20
5
MAX
0.8
0.4
3.0
2.5
1.4
1.1
0.85
+/- 10
-40
+/-10
+/-10
105
+/-10
-660
-75
0.8
0.8
0.8
+/-10
UNITS CONDITION
V DVDD = 5V
V DVDD = 3V
V
V DVDD = 5V
V DVDD = 3V
V DVDD = 5V
V DVDD = 3V
V DVDD = 5V or 3V
V
µA VIN = 0V or VDD
µA VIN = 0V, DVDD=5V, Internal Pullup
µA VIN = DVDD, DVDD=5V
µA VIN = 0V, DVDD=5V
µA VIN = DVDD, DVDD=5V, Internal Pull-Down
µA VIN = DVDD, DVDD=5V
µA VIN = 2V, DVDD=5V
µA VIN = 0.45V, DVDD=5V
pF All Digital Inputs
V DVDD = 5V, ISOURCE = 80 µA
V DVDD = 3V, ISOURCE = 20 µA
V ISINK = 8mA, SCLOCK, MOSI/SDATA
V ISINK = 10mA, P1.0, P1.1
V ISINK = 1.6mA, All Other Outputs
µA
pF
ms
ms
ms Controlled via WDCON SFR
us
PLLCON.7 = 0
us
us
us
us
PLLCON.7 = 1
us
us
ms
REV. PrB
-5-
5 Page 
PRELIMINARY TECHNICAL DATA
ADuC844
Pin No:
52-MQFP
41
Pin No:
56-CSP
44
Pin
Mnemonic
PSEN
42 45
ALE
43 à 46
49 à 52
46 à 49
52 à 55
P0.0 à P0.7
*I = Input, O = Output, S = Supply.
Type* Description
Program Store Enable, Logic Output. This output is a control signal that
enables the external program memory to the bus during external fetch
operations. It is active every six oscillator periods except during external data
memory accesses. This pin remains high during internal program execution.
PSEN can also be used to enable serial download mode when pulled low
through a resistor at the end of an external RESET assertion or as part of a
device power cycle.
Address Latch Enable, Logic Output. This output is used to latch the low byte
(and page byte for 24-bit data address space accesses) of the address to
external memory during external code or data memory access cycles. It is
activated every six oscillator periods except during an external data memory
access. It can be disabled by setting the PCON.4 bit in the PCON SFR.
I/O P0.0–P0.7, these pins are part of Port0 which is an 8-bit open-drain
bidirectional I/O port. Port 0 pins that have 1s written to them float and in that
state can be used as high impedance inputs. An external pull-up resistor will
be required on P0 outputs to force a valid logic high level externally. Port 0 is
also the multiplexed low-order address and data bus during accesses to
external program or data memory. In this application it uses strong internal
pull-ups when emitting 1s.
REV. PrB
-11-
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet ADUC844.PDF ] | |
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