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PDF ADSP-BF561SKBCZ500 Data sheet ( Hoja de datos )
| Número de pieza | ADSP-BF561SKBCZ500 | |
| Descripción | Blackfin Embedded Symmetric Multi-Processor | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Preliminary Technical Data
FEATURES
Dual Symmetric 600 Mhz High Performance Blackfin Core
328 KBytes of On-chip Memory (See Memory Info on Page 3)
Each Blackfin Core Includes:
Two 16-Bit MACs, Two 40-Bit ALUs, Four 8-Bit Video ALUs,
40-Bit Shifter
RISC-Like Register and Instruction Model for Ease of Pro-
gramming and Compiler-Friendly Support
Advanced Debug, Trace, and Performance- Monitoring
0.8 - 1.2V core VDD with On-Chip Voltage Regulation
3.3V and 2.5V Tolerant I/O
256-Ball Mini BGA and 297-Ball PBGA Package Options
Blackfin® Embedded
Symmetric Multi-Processor
ADSP-BF561
PERIPHERALS
Two Parallel Input/Output Peripheral Interface Units Sup-
porting ITU-R 656 Video and Glueless Interface to ADI
Analog Front End ADCs
Two Dual Channel, Full Duplex Synchronous Serial Ports Sup-
porting Eight Stereo I2S Channels
Dual 16 Channel DMA Controllers and one internal memory
DMA controller
12 General Purpose 32-bit Timer/Counters, with PWM
Capability
SPI-Compatible Port
UART with Support for IrDA®
Dual Watchdog Timers
48 Programable Flags
On-Chip Phase Locked Loop Capable of 1x to 63x Frequency
Multiplication
IRQ CTRL/
TIMER
VOLTAGE
REGULATOR
B
B
IRQ CTRL/
TIMER
L1
INSTRUCTION
MEMORY
MMU
L1
DATA
MEMORY
L1
INSTRUCTION
MEMORY
MMU
L1
DATA
MEMORY
L2 SRAM
128 KBYTES
CORE SYSTEM / BUS INTERFACE
EAB
32
BOOT ROM
DMA
CONTROLLER1
DMA
CONTROLLER2
32
DAB
EXTERNAL PORT
FLASH/SDRAM CONTROL
PPI PPI
IMDMA
CONTROLLER
DAB
PAB 16
16
JTAG TEST
EMULATION
UART
IRDA®
SPI
SPORT0
SPORT1
GPIO
TIMERS
Figure 1. Functional Block Diagram
Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.
Rev. PrC
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel:781/329-4700
www.analog.com
Fax:781/326-8703 © 2004 Analog Devices, Inc. All rights reserved.
1 page  
Preliminary Technical Data
ADSP-BF561
0xFFFFFFFF
0xFFE0 0000
0xFFC00000
0xFFB01000
0xFFB00000
0xFFA14000
0xFFA10000
0xFFA04000
0xFFA00000
0xFF908000
0xFF904000
0xFF900000
0xFF808000
0xFF804000
0xFF800000
0xFEB2 0000
0xFEB0 0000
0xEF00 4000
0xEF00 0000
0x3000 0000
0x2C00 0000
0x2800 0000
0x2400 0000
0x2000 0000
Topof last SDRAMpage
0x0000 0000
COREAMEMORYMAP
COREBMEMORYMAP
COREMMRREGISTERS
COREMMRREGISTERS
SYSTEMMMRREGISTERS
RESERVED
L1SCRATCHPADSRAM(4K)
RESERVED
L1INSTRUCTIONSRAM/CACHE(16K)
RESERVED
L1INSTRUCTIONSRAM(16K)
RESERVED
RESERVED
L1DATABANKBSRAM/CACHE(16K)
L1DATABANKBSRAM(16K)
RESERVED
L1DATABANKASRAM/CACHE(16K)
L1DATABANKASRAM(16K)
RESERVED
RESERVED
L1 SCRATCHPADSRAM(4K)
RESERVED
L1 INSTRUCTIONSRAM/CACHE(16K)
RESERVED
L1 INSTRUCTIONSRAM(16K)
RESERVED
L1DATABANKBSRAM/CACHE(16K)
L1 DATABANKBSRAM(16K)
RESERVED
L1DATABANKASRAM/CACHE(16K)
L1 DATABANKASRAM(16K)
RESERVED
L2 SRAM(128K)
RESERVED
BOOTROM
RESERVED
ASYNCMEMORYBANK3
ASYNCMEMORYBANK2
ASYNCMEMORYBANK1
ASYNCMEMORYBANK0
RESERVED
SDRAMBANK3
SDRAMBANK2
SDRAMBANK1
SDRAMBANK0
0xFF800000
0xFF701000
0xFF700000
0xFF614000
0xFF610000
0xFF604000
0xFF600000
0xFF508000
0xFF504000
0xFF500000
0xFF408000
0xFF404000
0xFF400000
INTERNALMEMORY
EXTERNALMEMORY
Figure 3. Memory Map
The fourth on-chip memory system is the L2 SRAM memory
array which provides 128K bytes of high speed SRAM operating
at one half the bandwidth of the core, and slightly longer latency
than the L1 memory banks. The L2 memory is a unified instruc-
tion and data memory and can hold any mixture of code and
data required by the system design. The Blackfin cores share a
dedicated low-latency 64-bit wide data path port into the L2
SRAM memory.
Each Blackfin core processor has its own set of core Memory
Mapped Registers (MMRs) but share the same system MMR
registers and 128 KB L2 SRAM memory.
External (Off-Chip) Memory
The ADSP-BF561 external memory is accessed via the External
Bus Interface Unit (EBIU). This interface provides a glueless
connection to up to four banks of synchronous DRAM
(SDRAM) as well as up to four banks of asynchronous memory
devices including flash, EPROM, ROM, SRAM, and memory
mapped I/O devices.
The PC133-compliant SDRAM controller can be programmed
to interface to up to four banks of SDRAM, with each bank con-
taining between 16M bytes and 128M bytes providing access to
up to 512M bytes of SDRAM. Each bank is independently pro-
grammable and is contiguous with adjacent banks regardless of
the sizes of the different banks or their placement. This allows
flexible configuration and upgradability of system memory
while allowing the core to view all SDRAM as a single, contigu-
ous, physical address space.
The asynchronous memory controller can also be programmed
to control up to four banks of devices with very flexible timing
parameters for a wide variety of devices. Each bank occupies a
Rev. PrC | Page 5 of 52 | April 2004
5 Page 
Preliminary Technical Data
Entire Field Mode
In this mode, the entire incoming bitstream is read in through
the PPI. This includes active video, control preamble sequences,
and ancillary data that may be embedded in horizontal and ver-
tical blanking intervals.
Though not explicitly supported, ITU,-656 output functionality
can be achieved by setting up the entire frame structure (includ-
ing active video, blanking and control information) in memory
and streaming the data out of the PPI in a frame sync-less mode.
The processor’s 2D DMA features facilitate this transfer by
allowing the static frame buffer (blanking and control codes) to
be placed in memory once, and simply updating the active video
information on per-frame basis.
These modes support ADC/DAC connections, as well as video
communication with hardware signaling. Many of the modes
support more than one level of frame synchronization. If
desired, a programmable delay can be inserted between asser-
tion of a frame sync and reception/transmission of data.
DYNAMIC POWER MANAGEMENT
The ADSP-BF561 provides four operating modes, each with a
different performance/power profile. In addition, Dynamic
Power Management provides the control functions to dynami-
cally alter the processor core supply voltage, further reducing
power dissipation. Control of clocking to each of the ADSP-
BF561 peripherals also reduces power consumption. See Table 3
for a summary of the power settings for each mode.
Full-On Operating Mode – Maximum Performance
In the Full-On mode, the PLL is enabled and is not bypassed,
providing capability for maximum operational frequency. This
is the default execution state in which maximum performance
can be achieved. The processor cores and all enabled peripherals
run at full speed.
Active Operating Mode – Moderate Power Savings
In the Active mode, the PLL is enabled but bypassed. Because
the PLL is bypassed, the processor’s core clock (CCLK) and sys-
tem clock (SCLK) run at the input clock (CLKIN) frequency. In
this mode, the CLKIN to CCLK multiplier ratio can be changed,
although the changes are not realized until the Full-On mode is
entered. DMA access is available to appropriately configured L1
memories.
In the Active mode, it is possible to disable the PLL through the
PLL Control register (PLL_CTL). If disabled, the PLL must be
re-enabled before transitioning to the Full-On or Sleep modes.
Table 3. Power Settings
Mode
Full On
Active
PLL PLL
Core System Core
Bypassed Clock Clock Power
(CCLK) (SCLK)
Enabled No
Enabled Enabled On
Enabled/ Yes
Disabled
Enabled Enabled On
ADSP-BF561
Table 3. Power Settings (Continued)
Mode PLL PLL
Core System Core
Bypassed Clock Clock Power
(CCLK) (SCLK)
Sleep
Enabled –
Disabled Enabled On
Deep Sleep Disabled –
Disabled Disabled On
Hibernate Disabled –
Disabled Disabled Off
Hibernate Operating Mode—Maximum Static Power
Savings
The Hibernate mode maximizes static power savings by dis-
abling the voltage and clocks to the processor core (CCLK) and
to all the synchronous peripherals (SCLK). The internal voltage
regulator for the processor can be shut off by writing b#00 to the
FREQ bits of the VR_CTL register. This disables both CCLK
and SCLK. Furthermore, it sets the internal power supply volt-
age (VDDINT) to 0 V to provide the lowest static power
dissipation. Any critical information stored internally (memory
contents, register contents, etc.) must be written to a non-vola-
tile storage device prior to removing power if the processor state
is to be preserved. Since VDDEXT is still supplied in this mode, all
of the external pins tri-state, unless otherwise specified. This
allows other devices that may be connected to the processor to
have power still applied without drawing unwanted current.
The internal supply regulator can be woken up by asserting the
RESET pin.
Sleep Operating Mode—High Dynamic Power Savings
The Sleep mode reduces power dissipation by disabling the
clock to the processor core (CCLK). The PLL and system clock
(SCLK), however, continue to operate in this mode. Typically an
external event will wake up the processor. When in the Sleep
mode, assertion of wakeup will cause the processor to sense the
value of the BYPASS bit in the PLL Control register (PLL_CTL).
When in the Sleep mode, system DMA access to L1 memory is
not supported.
Deep Sleep Operating Mode—Maximum Dynamic Power
Savings
The Deep Sleep mode maximizes power savings by disabling the
clocks to the processor cores (CCLK) and to all synchronous
peripherals (SCLK). Asynchronous peripherals will not be able
to access internal resources or external memory. This powered-
down mode can only be exited by assertion of the reset interrupt
(RESET). If BYPASS is disabled, the processor will transition to
the Full On mode. If BYPASS is enabled, the processor will tran-
sition to the Active mode.
Power Savings
As shown in Table 4, the ADSP-BF561 supports two different
power domains. The use of multiple power domains maximizes
flexibility, while maintaining compliance with industry stan-
dards and conventions. By isolating the internal logic of the
ADSP-BF561 into its own power domain, separate from the I/O,
Rev. PrC | Page 11 of 52 | April 2004
11 Page | ||
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