|
|
PDF ADSP-21MOD870-000 Data sheet ( Hoja de datos )
| Número de pieza | ADSP-21MOD870-000 | |
| Descripción | Internet Gateway Processor | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de ADSP-21MOD870-000 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
a
Internet Gateway Processor
FEATURES
PERFORMANCE
Complete Single-Chip Internet Gateway Processor (No
External Memory Required)
Implements V.34/V.90 Data/FAX Modem Including
Controller and Datapump
19 ns Instruction Cycle Time @ 3.3 V, 52 MIPS Sustained
Performance
Open Architecture Platform Extensible to Voice Over IP
and Other Applications
Low Power Dissipation, 80 mW (Typical) for Digital
Modem
Power-Down Mode Featuring Low CMOS Standby
Power Dissipation
INTEGRATION
ADSP-2100 Family Code Compatible, with Instruction
Set Extensions
160K Bytes of On-Chip RAM, Configured as 32K Words
On-Chip Program Memory RAM and 32K Words On-
Chip Data Memory RAM
Dual Purpose Program Memory for Both Instruction
and Data Storage
Independent ALU, Multiplier/Accumulator and Barrel
Shifter Computational Units
Two Independent Data Address Generators
Powerful Program Sequencer Provides Zero Overhead
Looping Conditional Instruction Execution
Programmable 16-Bit Interval Timer with Prescaler
100-Lead LQFP with 0.4 Square Inch (256 mm2) Footprint
SYSTEM INTERFACE
16-Bit Internal DMA Port for High Speed Access to On-
Chip Memory (Mode Selectable)
Two Double-Buffered Serial Ports with Companding
Hardware and Automatic Data Buffering
Programmable Multichannel Serial Port Supports
24/32 Channels
Automatic Booting of On-Chip Program Memory
Through Internal DMA Port
Six External Interrupts
13 Programmable Flag Pins Provide Flexible System
Signaling
ICE-Port™ Emulator Interface Supports Debugging in
Final Systems
ICE-Port is a trademark of Analog Devices, Inc.
All other trademarks are the property of their respective holders.
ADSP-21mod870
FUNCTIONAL BLOCK DIAGRAM
DATA ADDRESS
GENERATORS
DAG 1 DAG 2
PROGRAM
SEQUENCER
POWER-DOWN
CONTROL
MEMORY
16K؋24 PM
8K؋24 OVERLAY 1
8K؋24 OVERLAY 2
16K؋16 DM
8K؋16 OVERLAY 1
8K؋16 OVERLAY 2
PROGRAMMABLE
I/O
AND
FLAGS
FULL MEMORY
MODE
EXTERNAL
ADDRESS
BUS
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
ARITHMETIC UNITS
ALU MAC SHIFTER
ADSP-2100 BASE
ARCHITECTURE
SERIAL PORTS
SPORT 0 SPORT 1
TIMER
EXTERNAL
DATA
BUS
BYTE DMA
CONTROLLER
OR
EXTERNAL
DATA
BUS
INTERNAL
DMA
PORT
HOST MODE
GENERAL DESCRIPTION
The ADSP-21mod870 is a single-chip Internet gateway pro-
cessor optimized for implementation of a complete V.34/56K
modem. All data pump and controller functions can be imple-
mented on a single chip, offering the lowest power consumption
and highest possible modem port density.
The ADSP-21mod870, shown in the Functional Block Dia-
gram, combines the ADSP-2100 family base architecture (three
computational units, data address generators and a program
sequencer) with two serial ports, a 16-bit internal DMA port, a
byte DMA port, a programmable timer, Flag I/O, extensive
interrupt capabilities and on-chip program and data memory.
The ADSP-21mod870 integrates 160K bytes of on-chip
memory configured as 32K words (24-bit) of program RAM,
and 32K words (16-bit) of data RAM. Power-down circuitry is
also provided to meet the low power needs of battery operated
portable equipment. The ADSP-21mod870 is available in
100-lead LQFP package.
Fabricated in a high speed, low power, CMOS process, the
ADSP-21mod870 operates with a 19 ns instruction cycle time.
Every instruction can execute in a single processor cycle.
The ADSP-21mod870’s flexible architecture and comprehen-
sive instruction set allow the processor to perform multiple
operations in parallel. In one processor cycle the ADSP-21mod870
can:
• Generate the next program address
• Fetch the next instruction
• Perform one or two data moves
• Update one or two data address pointers
• Perform a computational operation
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
1 page  
ADSP-21mod870
Memory Interface Pins
The ADSP-21mod870 processor can be used in one of two
modes: Full Memory Mode, which allows BDMA operation
with full external overlay memory and I/O capability, or Host
Mode, which allows IDMA operation with limited external
addressing capabilities. The operating mode is determined by
the state of the Mode C pin during RESET and cannot be
changed while the processor is running.
Full Memory Mode Pins (Mode C = 0)
Pin Name
A13:0
D23:0
#
of
Pins
14
24
Input/
Output
O
I/O
Function
Address Output Pins for Pro-
gram, Data, Byte and I/O Spaces
Data I/O Pins for Program,
Data, Byte and I/O Spaces
(8 MSBs Are Also Used as
Byte Memory Addresses)
Host Mode Pins (Mode C = 1)
#
of Input/
Pin Name Pins Output Function
IAD15:0
A0
D23:8
IWR
IRD
IAL
IS
IACK
16
1
16
1
1
1
1
1
I/O
O
I/O
I
I
I
I
O
IDMA Port Address/Data Bus
Address Pin for External I/O,
Program, Data, or Byte Access
Data I/O Pins for Program,
Data Byte and I/O Spaces
IDMA Write Enable
IDMA Read Enable
IDMA Address Latch Pin
IDMA Select
IDMA Port Acknowledge
Configurable in Mode D; Open
Drain
In Host Mode, external peripheral addresses can be decoded using the A0,
CMS, PMS, DMS and IOMS signals.
Terminating Unused Pin
The following table shows the recommendations for terminating
unused pins.
Pin Terminations
Pin
Name
I/O
3-State
(Z)
Reset
State
Hi-Z*
Caused
By
Unused
Configuration
XTAL
CLKOUT
A13:1 or
IAD12:0
A0
D23:8
D7 or
IWR
D6 or
IRD
D5 or
IAL
I
O
O (Z)
I/O (Z)
O (Z)
I/O (Z)
I/O (Z)
I
I/O (Z)
I
I/O (Z)
I
I
O
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
I
Hi-Z
I
Hi-Z
I
BR, EBR
IS
BR, EBR
BR, EBR
BR, EBR
BR, EBR
BR, EBR
BR, EBR
Float
Float
Float
Float
Float
Float
Float
High (Inactive)
Float
High (Inactive)
Float
Low (Inactive)
D4 or
IS
D3 or
IACK
D2:0 or
IAD15:13
PMS
DMS
BMS
IOMS
CMS
RD
WR
BR
BG
BGH
IRQ2/PF7
I/O (Z)
I
I/O (Z)
**
I/O (Z)
I/O (Z)
O (Z)
O (Z)
O (Z)
O (Z)
O (Z)
O (Z)
O (Z)
I
O (Z)
O (Z)
I/O (Z)
Hi-Z
I
Hi-Z
**
Hi-Z
Hi-Z
O
O
O
O
O
O
O
I
O
O
I
IRQL1/PF6 I/O (Z) I
IRQL0/PF5 I/O (Z) I
IRQE/PF4 I/O (Z) I
SCLK0
I/O
RFS0
DR0
TFS0
DT0
SCLK1
I/O
I
I/O
O
I/O
RFS1/IRQ0
DR1/FI
TFS1/IRQ1
DT1/FO
EE
EBR
EBG
ERESET
EMS
EINT
ECLK
ELIN
ELOUT
I/O
I
I/O
O
I
I
O
I
O
I
I
I
O
I
I
I
O
O
I
I
I
O
O
I
I
O
I
O
I
I
I
O
BR, EBR
BR, EBR
BR, EBR
IS
BR, EBR
BR, EBR
BR, EBR
BR, EBR
BR, EBR
BR, EBR
BR, EBR
EE
EE
Float
High (Inactive)
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
High (Inactive)
Float
Float
Input = High (Inactive)
or Program as Output,
Set to 1, Let Float
Input = High (Inactive)
or Program as Output,
Set to 1, Let Float
Input = High (Inactive)
or Program as Output,
Set to 1, Let Float
Input = High (Inactive)
or Program as Output,
Set to 1, Let Float
Input = High or Low,
Output = Float
High or Low
High or Low
High or Low
Float
Input = High or Low,
Output = Float
High or Low
High or Low
High or Low
Float
NOTES
**Hi-Z = High Impedance.
**Determined by MODE D pin:
Mode D = 0 and in host mode: IACK is an active, driven signal and cannot
be “wire ORed.”
Mode D = 1 and in host mode: IACK is an open source and requires an
external pull-down, but multiple IACK pins can be “wire ORed” together.
1. If the CLKOUT pin is not used, turn it OFF.
2. If the Interrupt/Programmable Flag pins are not used, there are two options:
Option 1: When these pins are configured as INPUTS at reset and function
as interrupts and input flag pins, pull the pins High (inactive).
Option 2: Program the unused pins as OUTPUTS, set them to 1, and let
them float.
3. All bidirectional pins have three-stated outputs. When the pins is configured
as an output, the output is Hi-Z (high impedance).
4. CLKIN, RESET, and PF3:0 are not included in the table because these pins
must be used.
REV. 0
–5–
5 Page 
ADSP-21mod870
Unused bits in the 8-bit data memory formats are filled with 0s.
The BIAD register field is used to specify the starting address
for the on-chip memory involved with the transfer. The 14-bit
BEAD register specifies the starting address for the external byte
memory space. The 8-bit BMPAGE register specifies the start-
ing page for the external byte memory space. The BDIR register
field selects the direction of the transfer. Finally the, 14-bit
BWCOUNT register specifies the number of DSP words to
transfer and initiates the BDMA circuit transfers.
BTYPE
00
01
10
11
Table VI. Data Formats
Internal
Memory Space
Program Memory
Data Memory
Data Memory
Data Memory
Word Size
24
16
8
8
Alignment
Full Word
Full Word
MSBs
LSBs
BDMA accesses can cross page boundaries during sequential
addressing. A BDMA interrupt is generated on the completion
of the number of transfers specified by the BWCOUNT register.
The BWCOUNT register is updated after each transfer so it can
be used to check the status of the transfers. When it reaches zero,
the transfers have finished and a BDMA interrupt is generated.
The BMPAGE and BEAD registers must not be accessed by the
processor during BDMA operations.
The source or destination of a BDMA transfer will always be
on-chip program or data memory.
When the BWCOUNT register is written with a nonzero value,
the BDMA circuit starts executing byte memory accesses with
wait states set by BMWAIT. These accesses continue until the
count reaches zero. When enough accesses have occurred to
create a destination word, it is transferred to or from on-chip
memory. The transfer takes one processor cycle. Processor
accesses to external memory have priority over BDMA byte
memory accesses.
The BDMA Context Reset bit (BCR) controls whether the
processor is held off while the BDMA accesses are occurring.
Setting the BCR bit to 0 allows the processor to continue opera-
tions. Setting the BCR bit to 1 causes the processor to stop
execution while the BDMA accesses are occurring, to clear the
context of the processor, and start execution at address 0 when
the BDMA accesses have completed. The BDMA overlay bits
specify the OVLAY memory blocks to be accessed for internal
memory.
Internal Memory DMA Port (IDMA Port; Host Memory
Mode)
The IDMA Port provides an efficient means of communication
between a host system and the ADSP-21mod870. The port is
used to access the on-chip program memory and data memory
of the processor with only one processor cycle per word over-
head. The IDMA port cannot be used, however, to write to the
processor’s memory-mapped control registers. A typical IDMA
transfer process is described as follows:
1. Host starts IDMA transfer.
2. Host checks IACK control line to see if the processor is busy.
3. Host uses IS and IAL control lines to latch either the DMA
starting address (IDMAA) or the PM/DM OVLAY selection
into the processor’s IDMA control registers.
If IAD[15] = 1, the value of IAD[7:0] represents the IDMA
overlay: Bits 14:8 must be set to 0.
If IAD[15] = 0, the value of IAD[13:0] represents the start-
ing address of internal memory to be accessed and IAD[14]
reflects PM or DM for access.
4. Host uses IS and IRD (or IWR) to read (or write) processor
internal memory (PM or DM).
5. Host checks IACK line to see if the processor has completed
the previous IDMA operation.
6. Host ends IDMA transfer.
The IDMA port has a 16-bit multiplexed address and data bus
and supports 24-bit program memory. The IDMA port is com-
pletely asynchronous and can be written to while the ADSP-
21mod870 is operating at full speed.
The processor memory address is latched and is then automati-
cally incremented after each IDMA transaction. An external
device can therefore access a block of sequentially addressed
memory by specifying only the starting address of the block.
This increases throughput as the address does not have to be
sent for each memory access.
IDMA Port access occurs in two phases. The first is the IDMA
Address Latch cycle. When the acknowledge is asserted, a 14-bit
address and 1-bit destination type can be driven onto the bus by
an external device. The address specifies an on-chip memory
location; the destination type specifies whether it is a DM or
PM access. The falling edge of the address latch signal latches
this value into the IDMAA register.
Once the address is stored, data can then be either read from, or
written to, the ADSP-21mod870’s on-chip memory. Asserting
the select line (IS) and the appropriate read or write line (IRD
and IWR respectively) signals the ADSP-21mod870 that a par-
ticular transaction is required. In either case, there is a one-
processor-cycle delay for synchronization. The memory access
consumes one additional processor cycle.
Once an access has occurred, the latched address is automati-
cally incremented, and another access can occur.
Through the IDMAA register, the processor can also specify the
starting address and data format for DMA operation. Asserting
the IDMA port select (IS) and address latch enable (IAL)
directs the ADSP-21mod870 to write the address onto the
IAD[14:0] bus into the IDMA Control Register. If IAD[15]
is set to 0, IDMA latches the address. If IAD[15] is set to 1,
IDMA latches OVLAY memory. This register, shown below, is
memory mapped at address DM (0x3FE0). Note that the latched
address (IDMAA) cannot be read back by the host.
REV. 0
–11–
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ADSP-21MOD870-000.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| ADSP-21MOD870-000 | Internet Gateway Processor | Analog Devices |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |