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PDF ADSP-21990BBC Data sheet ( Hoja de datos )
| Número de pieza | ADSP-21990BBC | |
| Descripción | Mixed Signal DSP Controller | |
| Fabricantes | Analog Devices | |
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a
Mixed Signal DSP Controller
ADSP-21990
KEY FEATURES
ADSP-219x, 16-Bit, Fixed Point DSP Core with up to
160 MIPS Sustained Performance
8K Words of On-Chip RAM, Configured as 4K Words On-
Chip 24-Bit Program RAM and 4K Words On-Chip
16-Bit Data RAM
External Memory Interface
Dedicated Memory DMA Controller for Data/Instruction
Transfer between Internal/External Memory
Programmable PLL and Flexible Clock Generation
Circuitry Enables Full Speed Operation from Low
Speed Input Clocks
IEEE JTAG Standard 1149.1 Test Access Port Supports
On-Chip Emulation and System Debugging
8-Channel, 14-Bit Analog-to-Digital Converter System,
with up to 20 MSPS Sampling Rate (at 160 MHz Core
Clock Rate)
Three Phase 16-Bit Center Based PWM Generation Unit
with 12.5 ns Resolution at 160 MHz Core Clock (CCLK)
Rate
Dedicated 32-Bit Encoder Interface Unit with
Companion Encoder Event Timer
Dual 16-Bit Auxiliary PWM Outputs
16 General-Purpose Flag I/O Pins
Three Programmable 32-Bit Interval Timers
SPI Communications Port with Master or Slave
Operation
Synchronous Serial Communications Port (SPORT)
Capable of Software UART Emulation
Integrated Watchdog Timer
Dedicated Peripheral Interrupt Controller with Software
Priority Control
Multiple Boot Modes
Precision 1.0 V Voltage Reference
FUNCTIONAL BLOCK DIAGRAM
CLOCK
GENERATOR/PLL
JTAG
TEST AND
EMULATION
ADSP-219x
DSP CORE
I/O
BUS
I/O REGISTERS
4K ؋ 24
PM RAM
4K ؋ 16
DM RAM
4K ؋ 24
PM ROM
PM ADDRESS/DATA
DM ADDRESS/DATA
SPI
EXTERNAL
MEMORY
INTERFACE
(EMI)
ADDRESS
DATA
CONTROL
SPORT
MEMORY DMA
CONTROLLER
PWM
GENERATION
UNIT
ENCODER
INTERFACE
UNIT
(AND EET)
AUXILIARY
PWM
UNIT
TIMER 0
TIMER 1
TIMER 2
FLAG
I/O
WATCHDOG
TIMER
INTERRUPT
CONTROLLER
(ICNTL)
ADC
CONTROL
POR
PIPELINE
FLASH ADC
VREF
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel:781/329-4700
www.analog.com
Fax:781/326-8703
© 2003 Analog Devices, Inc. All rights reserved.
1 page  
NOTE: The physical external memory addresses are limited by
20 address lines, and are determined by the external data width
and packing of the external memory space. The Strobe signals
(MS3-0) can be programmed to allow the user to change starting
page addresses at run time.
0x00 0000
0x00 0FFF BLOCK 0: 4K ؋ 24-BIT RAM
0x00 1000
0x00 7FFF
RESERVED (28K)
0x00 8000
BLOCK 1: 4K ؋ 16-BIT RAM
0x00 8FFF
0x00 9000
0x00 FFFF
RESERVED (28K)
0x01 0000
EXTERNAL MEMORY
(4M – 64K)
0x40 0000
EXTERNAL MEMORY
0x80 0000
EXTERNAL MEMORY
0xC0 0000
0xFF 0000
0xFF 0FFF
0xFF 1000
0xFF FFFF
EXTERNAL MEMORY
(4M – 64K)
BLOCK 2: 4K ؋ 24-BIT
PM ROM
UNUSED ON-CHIP
MEMORY (60K)
PAGE 0 (64K) ON-CHIP
(0 WAIT STATE)
PAGES 1 TO 63
BANK 0 (OFF-CHIP) MS0
PAGES 64 TO 127
MS1
BANK 1 (OFF-CHIP)
PAGES 128 TO 191
BANK 2 (OFF-CHIP)
MS2
PAGES 192 TO 254
BANK 0 (OFF-CHIP) MS3
PAGE 255
(ON-CHIP)
Figure 2. Core Memory Map at Reset
Internal (On-Chip) Memory
The ADSP-21990 unified program and data memory space
consists of 16M locations that are accessible through two 24-bit
address buses, the PMA and DMA buses. The DSP uses slightly
different mechanisms to generate a 24-bit address for each bus.
The DSP has three functions that support access to the full
memory map.
• The DAGs generate 24-bit addresses for data fetches from
the entire DSP memory address range. Because DAG
index (address) registers are 16 bits wide and hold the
lower 16 bits of the address, each of the DAGs has its own
8-bit page register (DMPGx) to hold the most significant
eight address bits. Before a DAG generates an address,
the program must set the DAG DMPGx register to the
appropriate memory page. The DMPG1 register is also
used as a page register when accessing external memory.
The program must set DMPG1 accordingly, when
accessing data variables in external memory. A “C”
program macro is provided for setting this register.
• The program sequencer generates the addresses for
instruction fetches. For relative addressing instructions,
the program sequencer bases addresses for relative jumps,
calls, and loops on the 24-bit Program Counter (PC). In
direct addressing instructions (two word instructions),
ADSP-21990
the instruction provides an immediate 24-bit address
value. The PC allows linear addressing of the full 24-bit
address range.
• For indirect jumps and calls that use a 16-bit DAG
address register for part of the branch address, the
Program Sequencer relies on an 8-bit Indirect Jump page
(IJPG) register to supply the most significant eight
address bits. Before a cross page jump or call, the program
must set the program sequencer IJPG register to the
appropriate memory page.
The ADSP-21990 has 4K word of on-chip ROM that holds boot
routines. The DSP starts executing instructions from the on-chip
boot ROM, which starts the boot process. See Booting Modes
on Page 13. The on-chip boot ROM is located on Page 255 in
the DSP memory space map, starting at address 0xFF0000.
External (Off-Chip) Memory
Each of the ADSP-21990 off-chip memory spaces has a separate
control register, so applications can configure unique access
parameters for each space. The access parameters include read
and write wait counts, wait state completion mode, I/O clock
divide ratio, write hold time extension, strobe polarity, and data
bus width. The core clock and peripheral clock ratios influence
the external memory access strobe widths. See Clock Signals on
Page 12. The off-chip memory spaces are:
• External memory space (MS3–0 pins)
• I/O memory space (IOMS pin)
• Boot memory space (BMS pin)
All of the above off-chip memory spaces are accessible through
the External Port, which can be configured for 8-bit or 16-bit
data widths.
External Memory Space
External memory space consists of four memory banks. These
banks can contain a configurable number of 64 K word pages. At
reset, the page boundaries for external memory have Bank0 con-
taining pages 1 to 63, Bank1 containing pages 64 to 127, Bank2
containing pages 128 to 191, and Bank3 containing pages 192 to
254. The MS3-0 memory bank pins select Banks 3-0, respec-
tively. Both the ADSP-219x core and DMA capable peripherals
can access the DSP external memory space.
All accesses to external memory are managed by the External
Memory Interface Unit (EMI).
I/O Memory Space
The ADSP-21990 supports an additional external memory
called I/O memory space. The IO space consists of 256 pages,
each containing 1024 addresses. This space is designed to
support simple connections to peripherals (such as data convert-
ers and external registers) or to bus interface ASIC data registers.
The first 32K addresses (IO pages 0 to 31) are reserved for
on-chip peripherals. The upper 224K addresses (IO pages 32 to
255) are available for external peripheral devices. External I/O
pages have their own select pin (IOMS). The DSP instruction
set provides instructions for accessing I/O space.
REV. 0
–5–
5 Page 
ADSP-21990
Table 2. Interrupt Priorities/Addresses
Interrupt
Emulator (NMI)
—Highest Priority
Reset (NMI)
Power Down (NMI)
Loop and PC Stack
Emulation Kernel
User Assigned Interrupt
(USR0)
User Assigned Interrupt
(USR1)
User Assigned Interrupt
(USR2)
User Assigned Interrupt
(USR3)
User Assigned Interrupt
(USR4)
User Assigned Interrupt
(USR5)
User Assigned Interrupt
(USR6)
User Assigned Interrupt
(USR7)
User Assigned Interrupt
(USR8)
User Assigned Interrupt
(USR9)
User Assigned Interrupt
(USR10)
User Assigned Interrupt
(USR11)
—Lowest Priority
IMASK/
IRPTL
NA
Vector Address
NA
0 0x00 0000
1 0x00 0020
2 0x00 0040
3 0x00 0060
4 0x00 0080
5 0x00 00A0
6 0x00 00C0
7 0x00 00E0
8 0x00 0100
9 0x00 0120
10 0x00 0140
11 0x00 0160
12 0x00 0180
13 0x00 01A0
14 0x00 01C0
15 0x00 01E0
Peripheral Interrupt Controller
The Peripheral Interrupt Controller is a dedicated peripheral unit
of the ADSP-21990 (accessed via IO mapped registers). The
peripheral interrupt controller manages the connection of up to
32 peripheral interrupt requests to the DSP core.
For each peripheral interrupt source, there is a unique 4-bit code
that allows the user to assign the particular peripheral interrupt
to any one of the 12 user assignable interrupts of the embedded
ADSP-219x core. Therefore, the peripheral interrupt controller
of the ADSP-21990 contains eight, 16-bit Interrupt Priority
Registers (Interrupt Priority Register 0 (IPR0) to Interrupt
Priority Register 7 (IPR7)).
Each Interrupt Priority Register contains a four 4-bit codes; one
specifically assigned to each peripheral interrupt. The user may
write a value between 0x0 and 0xB to each 4-bit location in order
to effectively connect the particular interrupt source to the cor-
responding user assignable interrupt of the ADSP-219x core.
Writing a value of 0x0 connects the peripheral interrupt to the
USR0 user assignable interrupt of the ADSP-219x core while
writing a value of 0xB connects the peripheral interrupt to the
USR11 user assignable interrupt. The core interrupt USR0 is the
highest priority user interrupt, while USR11 is the lowest priority.
Writing a value between 0xC and 0xF effectively disables the
peripheral interrupt by not connecting it to any ADSP-219x core
interrupt input. The user may assign more than one peripheral
interrupt to any given ADSP-219x core interrupt. In that case,
the burden is on the user software in the interrupt vector table to
determine the exact interrupt source through reading status bits.
This scheme permits the user to assign the number of specific
interrupts that are unique to their application to the interrupt
scheme of the ADSP-219x core. The user can then use the
existing interrupt priority control scheme to dynamically control
the priorities of the 12 core interrupts.
Low Power Operation
The ADSP-21990 has four low power options that significantly
reduce the power dissipation when the device operates under
standby conditions. To enter any of these modes, the DSP
executes an IDLE instruction. The ADSP-21990 uses the con-
figuration of the PD, STCK, and STALL bits in the PLLCTL
register to select between the low power modes as the DSP
executes the IDLE instruction. Depending on the mode, an
IDLE shuts off clocks to different parts of the DSP in the different
modes. The low power modes are:
• Idle
• Power-Down Core
• Power-Down Core/Peripherals
• Power-Down All
Idle Mode
When the ADSP-21990 is in Idle mode, the DSP core stops
executing instructions, retains the contents of the instruction
pipeline, and waits for an interrupt. The core clock and peripheral
clock continue running.
To enter Idle mode, the DSP can execute the IDLE instruction
anywhere in code. To exit Idle mode, the DSP responds to an
interrupt and (after two cycles of latency) resumes executing
instructions.
Power-Down Core Mode
When the ADSP-21990 is in Power-Down Core mode, the DSP
core clock is off, but the DSP retains the contents of the pipeline
and keeps the PLL running. The peripheral bus keeps running,
letting the peripherals receive data.
To exit Power-Down Core mode, the DSP responds to an
interrupt and (after two cycles of latency) resumes executing
instructions.
Power-Down Core/Peripherals Mode
When the ADSP-21990 is in Power-Down Core/Peripherals
mode, the DSP core clock and peripheral bus clock are off, but
the DSP keeps the PLL running. The DSP does not retain the
contents of the instruction pipeline.The peripheral bus is
stopped, so the peripherals cannot receive data.
To exit Power-Down Core/Peripherals mode, the DSP responds
to an interrupt and (after five to six cycles of latency) resumes
executing instructions.
REV. 0
–11–
11 Page | ||
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