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PDF ADSP-2195 Data sheet ( Hoja de datos )
| Número de pieza | ADSP-2195 | |
| Descripción | DSP Microcomputer | |
| Fabricantes | Analog Devices | |
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Preliminary Technical Data
DSP Microcomputer
ADSP-2195
ADSP-219x DSP CORE FEATURES
6.25 ns Instruction Cycle Time (Internal), for up to
160 MIPS Sustained Performance
ADSP-218x Family Code Compatible with the Same
Easy -to-Use Algebraic Syntax
Single-Cycle Instruction Execution
Up to 16M words of Addressable Memory Space with
24 Bits of Addressing Width
Dual Purpose Program Memory for Both Instruction and
Data Storage
Fully Transparent Instruction Cache Allows Dual
Operand Fetches in Every Instruction Cycle
Unified Memory Space Permits Flexible Address
Generation, Using Two Independent DAG Units
Independent ALU, Multiplier/Accumulator, and Barrel
Shifter Computational Units with Dual 40-bit
Accumulators
Single-Cycle Context Switch between Two Sets of
Computational and DAG Registers
Parallel Execution of Computation and Memory
Instructions
Pipelined Architecture Supports Efficient Code
Execution at Speeds up to 160 MIPS
Register File Computations with All Nonconditional,
Nonparallel Computational Instructions
Powerful Program Sequencer Provides Zero-Overhead
Looping and Conditional Instruction Execution
Architectural Enhancements for Compiled C
Code Efficiency
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FUNCTIONAL BLOCK DIAGRAM
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This information applies to a product under development. Its characteristics
and specifications are subject to change without notice. Analog Devices
assumes no obligation regarding future manufacturing unless otherwise
agreed to in writing.
One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel:781/329-4700 World Wide Web Site: http://www.analog.com
Fax:781/326-8703
©Analog Devices,Inc., 2001
1 page  
35(/,0,1$5< 7(&+1,&$/ '$7$
September 2001 For current information contact Analog Devices at 800/262-5643
ADSP-2195
within 64K word boundaries of each of the 256 memory
pages, but these buffers may not cross page boundaries.
Secondary registers duplicate all the primary registers in the
DAGs; switching between primary and secondary registers
provides a fast context switch.
Efficient data transfer in the core is achieved with the use of
internal buses:
• Program Memory Address (PMA) Bus
• Program Memory Data (PMD) Bus
• Data Memory Address (DMA) Bus
• Data Memory Data (DMD) Bus
• DMA Address Bus
• DMA Data Bus
The two address buses (PMA and DMA) share a single
external address bus, allowing memory to be expanded
off-chip, and the two data buses (PMD and DMD) share a
single external data bus. Boot memory space and I/O
memory space also share the external buses.
Program memory can store both instructions and data, per-
mitting the ADSP-2195 to fetch two operands in a single
cycle, one from program memory and one from data
memory. The DSP’s dual memory buses also let the
ADSP-219x core fetch an operand from data memory and
the next instruction from program memory in a single cycle.
DSP Peripherals Architecture
The functional block diagram on page 1 shows the DSP’s
on-chip peripherals, which include the external memory
interface, Host port, serial ports, SPI-compatible ports,
UART port, JTAG test and emulation port, timers, flags,
and interrupt controller. These on-chip peripherals can
connect to off-chip devices as shown in Figure 1.
The ADSP-2195 has a 16-bit Host port with DMA capa-
bility that lets external Hosts access on-chip memory. This
24-pin parallel port consists of a 16-pin multiplexed
data/address bus and provides a low-service overhead data
move capability. Configurable for 8- or 16-bits, this port
provides a glueless interface to a wide variety of 8- and 16-bit
microcontrollers. Two chip-selects provide Hosts access to
the DSP’s entire memory map. The DSP is bootable
through this port.
The ADSP-2195 also has an external memory interface that
is shared by the DSP’s core, the DMA controller, and DMA
capable peripherals, which include the UART, SPORT0,
SPORT1, SPORT2, SPI0, SPI1, and the Host port. The
external port consists of a 16-bit data bus, a 22-bit address
bus, and control signals. The data bus is configurable to
provide an 8 or 16 bit interface to external memory. Support
for word packing lets the DSP access 16- or 24-bit words
from external memory regardless of the external data bus
width. When configured for an 8-bit interface, the unused
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Figure 1. ADSP-2195 System Diagram
eight lines provide eight programmable, bidirectional gen-
eral-purpose Programmable Flag lines, six of which can be
mapped to software condition signals.
The memory DMA controller lets the ADSP-2195 move
data and instructions from between memory spaces: inter-
nal-to-external, internal-to-internal, and external-to-
external. On-chip peripherals can also use this controller for
DMA transfers.
The ADSP-2195 can respond to up to seventeen interrupts
at any given time: three internal (stack, emulator kernel, and
power-down), two external (emulator and reset), and twelve
user-defined (peripherals) interrupts. Programmers assign
REV. PrA
This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
5
5 Page 
35(/,0,1$5< 7(&+1,&$/ '$7$
September 2001 For current information contact Analog Devices at 800/262-5643
ADSP-2195
The functional modes selected by HPCR [7:6] are as follows
(assuming active high signal):
• ACK Mode—Acknowledge is active on strobes; HACK
goes high from the leading edge of the strobe to indicate
when the access can complete. After the Host samples the
HACK active, it can complete the access by removing the
strobe.The host port then removes the HACK.
• Ready Mode—Ready active on strobes, goes low to insert
wait state during the access.If the host port can not
complete the access, it de-asserts the HACK/READY
line. In this case, the Host has to extend the access by
keeping the strobe asserted. When the Host samples the
HACK asserted, it can then proceed and complete the
access by de-asserting the strobe.
While in Address Cycle Control (ACC) mode and the ACK
or Ready acknowledge modes, the HACK is returned active
for any address cycle.
Host Port Chip Selects
There are two chip-select signals associated with the Host
Port: HCMS and HCIOMS. The Host Chip Memory
Select (HCMS) lets the Host select the DSP and directly
access the DSP’s internal/external memory space or boot
memory space. The Host Chip I/O Memory Select
(HCIOMS) lets the Host select the DSP and directly access
the DSP’s internal I/O memory space.
Before starting a direct access, the Host configures Host
port interface registers, specifying the width of external data
bus (8- or 16-bit) and the target address page (in the IJPG
register). The DSP generates the needed memory select
signals during the access, based on the target address. The
Host port interface combines the data from one, two, or
three consecutive Host accesses (up to one 24-bit value) into
a single DMA bus access to prefetch Host direct reads or to
post direct writes. During assembly of larger words, the Host
port interface asserts ACK for each byte access that does
not start a read or complete a write. Otherwise, the Host
port interface asserts ACK when it has completed the
memory access successfully.
DSP Serial Ports (SPORTs)
The ADSP-2195 incorporates three complete synchronous
serial ports (SPORT0, SPORT1, and SPORT2) for serial
and multiprocessor communications. The SPORTs
support the following features:
• Bidirectional operation—each SPORT has independent
transmit and receive pins.
• Buffered (8-deep) transmit and receive ports—each port
has a data register for transferring data words to and from
other DSP components and shift registers for shifting data
in and out of the data registers.
• Clocking—each transmit and receive port can either use
an external serial clock (≤75 MHz) or generate its own,
in frequencies ranging from 1144 Hz to 75 MHz.
• Word length—each SPORT supports serial data words
from 3 to 16 bits in length transferred in Big Endian
(MSB) or Little Endian (LSB) format.
• Framing—each transmit and receive port can run with or
without frame sync signals for each data word. Frame sync
signals can be generated internally or externally, active
high or low, and with either of two pulsewidths and early
or late frame sync.
• Companding in hardware—each SPORT can perform
A-law or µ-law companding according to ITU recommen-
dation G.711. Companding can be selected on the
transmit and/or receive channel of the SPORT without
additional latencies.
• DMA operations with single-cycle overhead—each
SPORT can automatically receive and transmit multiple
buffers of memory data, one data word each DSP cycle.
Either the DSP’s core or a Host processor can link or chain
sequences of DMA transfers between a SPORT and
memory. The chained DMA can be dynamically allocated
and updated through the DMA descriptors (DMA
transfer parameters) that set up the chain.
• Interrupts—each transmit and receive port generates an
interrupt upon completing the transfer of a data word or
after transferring an entire data buffer or buffers through
DMA.
• Multichannel capability—each SPORT supports the
H.100 standard.
Serial Peripheral Interface (SPI) Ports
The DSP has two SPI-compatible ports that enable the DSP
to communicate with multiple SPI-compatible devices.
These ports are multiplexed with SPORT2, so either
SPORT2 or the SPI ports are active, depending on the state
of the OPMODE pin during hardware reset.
The SPI interface uses three pins for transferring data: two
data pins (Master Output-Slave Input, MOSIx, and Master
Input-Slave Output, MISOx) and a clock pin (Serial Clock,
SCKx). Two SPI chip select input pins (SPISSx) let other
SPI devices select the DSP, and fourteen SPI chip select
output pins (SPIxSEL7–1) let the DSP select other SPI
devices. The SPI select pins are reconfigured Programmable
Flag pins. Using these pins, the SPI ports provide a full
duplex, synchronous serial interface, which supports both
master and slave modes and multimaster environments.
Each SPI port’s baud rate and clock phase/polarities are
programmable (see Figure 4), and each has an integrated
DMA controller, configurable to support both transmit and
receive data streams. The SPI’s DMA controller can only
service unidirectional accesses at any given time.
SPI Clock Rate = -2----×-----S-H---P--C--I--B-L----KA-----U-----D---
Figure 4. SPI Clock Rate Calculation
REV. PrA
This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
11
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