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PDF ADSP-2184LBST-160 Data sheet ( Hoja de datos )
| Número de pieza | ADSP-2184LBST-160 | |
| Descripción | DSP Microcomputer | |
| Fabricantes | Analog Devices | |
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a
DSP Microcomputer
ADSP-2184L
FEATURES
PERFORMANCE
25 ns Instruction Cycle Time 40 MIPS Sustained
Performance
Single-Cycle Instruction Execution
Single-Cycle Context Switch
3-Bus Architecture Allows Dual Operand Fetches in
Every Instruction Cycle
Multifunction Instructions
Power-Down Mode Featuring Low CMOS Standby
Power Dissipation with 400 Cycle Recovery from
Power-Down Condition
Low Power Dissipation in Idle Mode
INTEGRATION
ADSP-2100 Family Code Compatible, with Instruction
Set Extensions
20K Bytes of On-Chip RAM, Configured as
4K Words On-Chip Program Memory RAM and
4K Words On-Chip Data Memory RAM
Dual Purpose Program Memory for Both Instruction
and Data Storage
Independent ALU, Multiplier/Accumulator and Barrel
Shifter Computational Units
Two Independent Data Address Generators
Powerful Program Sequencer Provides
Zero Overhead Looping Conditional Instruction
Execution
Programmable 16-Bit Interval Timer with Prescaler
100-Lead LQFP
SYSTEM INTERFACE
16-Bit Internal DMA Port for High Speed Access to
On-Chip Memory (Mode Selectable)
4 MByte Byte Memory Interface for Storage of Data
Tables and Program Overlays
8-Bit DMA to Byte Memory for Transparent Program
and Data Memory Transfers (Mode Selectable)
I/O Memory Interface with 2048 Locations Supports
Parallel Peripherals (Mode Selectable)
Programmable Memory Strobe and Separate I/O Memory
Space Permits “Glueless” System Design
(Mode Selectable)
Programmable Wait State Generation
Two Double-Buffered Serial Ports with Companding
Hardware and Automatic Data Buffering
Automatic Booting of On-Chip Program Memory from
Byte-Wide External Memory, e.g., EPROM, or
Through Internal DMA Port
ICE-Port is a trademark of Analog Devices, Inc.
All other trademarks are the property of their respective holders.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
FUNCTIONAL BLOCK DIAGRAM
DATA ADDRESS
GENERATORS PROGRAM
SEQUENCER
DAG 1 DAG 2
POWER-DOWN
CONTROL
MEMORY
4K ؋ 24 4K ؋ 16
PROGRAM DATA
MEMORY MEMORY
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
ARITHMETIC UNITS
ALU MAC SHIFTER
ADSP-2100 BASE
ARCHITECTURE
SERIAL PORTS
SPORT 0 SPORT 1
PROGRAMMABLE
I/O
AND
FLAGS
FULL MEMORY
MODE
EXTERNAL
ADDRESS
BUS
EXTERNAL
DATA
BUS
BYTE DMA
CONTROLLER
TIMER
OR
EXTERNAL
DATA
BUS
INTERNAL
DMA
PORT
HOST MODE
Six External Interrupts
13 Programmable Flag Pins Provide Flexible System
Signaling
UART Emulation through Software SPORT Reconfiguration
ICE-Port™ Emulator Interface Supports Debugging
in Final Systems
GENERAL DESCRIPTION
The ADSP-2184L is a single-chip microcomputer optimized for
digital signal processing (DSP) and other high speed numeric
processing applications.
The ADSP-2184L combines the ADSP-2100 family base archi-
tecture (three computational units, data address generators and
a program sequencer) with two serial ports, a 16-bit internal
DMA port, a byte DMA port, a programmable timer, Flag I/O,
extensive interrupt capabilities and on-chip program and data
memory.
The ADSP-2184L integrates 20K bytes of on-chip memory
configured as 4K words (24-bit) of program RAM and 4K
words (16-bit) of data RAM. Power-down circuitry is also pro-
vided to meet the low power needs of battery operated portable
equipment. The ADSP-2184L is available in a 100-lead LQFP
package.
In addition, the ADSP-2184L supports instructions that include
bit manipulations—bit set, bit clear, bit toggle, bit test—ALU
constants, multiplication instruction (x squared), biased round-
ing, result free ALU operations, I/O memory transfers and
global interrupt masking for increased flexibility.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
1 page  
ADSP-2184L
To minimize power consumption during power-down, configure
the programmable flag as an output when connected to a three-
stated buffer. This ensures that the pin will be held at a constant
level and not oscillate should the three-state driver’s level hover
around the logic switching point.
Interrupts
The interrupt controller allows the processor to respond to the
thirteen possible interrupts (eleven of which can be enabled
at any one time), and RESET with minimum overhead. The
ADSP-2184L provides four dedicated external interrupt input
pins, IRQ2, IRQL0, IRQL1 and IRQE (shared with the PF7:4
pins). In addition, SPORT1 may be reconfigured for IRQ0,
IRQ1, FLAG_IN and FLAG_OUT, for a total of six external
interrupts. The ADSP-2184L also supports internal interrupts
from the timer, the byte DMA port, the two serial ports, soft-
ware and the power-down control circuit. The interrupt levels
are internally prioritized and individually maskable (except
power-down and RESET). The IRQ2, IRQ0 and IRQ1 input
pins can be programmed to be either level- or edge-sensitive.
IRQL0 and IRQL1 are level-sensitive and IRQE is edge-sensitive.
The priorities and vector addresses of all interrupts are shown in
Table I.
Table I. Interrupt Priority and Interrupt Vector Addresses
Source Of Interrupt
RESET (or Power-Up with
PUCR = 1)
Power-Down (Nonmaskable)
IRQ2
IRQL1
IRQL0
SPORT0 Transmit
SPORT0 Receive
IRQE
BDMA Interrupt
SPORT1 Transmit or IRQ1
SPORT1 Receive or IRQ0
Timer
Interrupt Vector Address (Hex)
0000 (Highest Priority)
002C
0004
0008
000C
0010
0014
0018
001C
0020
0024
0028 (Lowest Priority)
Interrupt routines can either be nested, with higher priority
interrupts taking precedence, or processed sequentially. Inter-
rupts can be masked or unmasked with the IMASK register.
Individual interrupt requests are logically ANDed with the bits
in IMASK; the highest priority unmasked interrupt is then
selected. The power-down interrupt is nonmaskable.
The ADSP-2184L masks all interrupts for one instruction cycle
following the execution of an instruction that modifies the
IMASK register. This does not affect serial port autobuffering
or DMA transfers.
The interrupt control register, ICNTL, controls interrupt nest-
ing and defines the IRQ0, IRQ1 and IRQ2 external interrupts to
be either edge- or level-sensitive. The IRQE pin is an external
edge-sensitive interrupt and can be forced and cleared. The
IRQL0 and IRQL1 pins are external level-sensitive interrupts.
The IFC register is a write-only register used to force and clear
interrupts.
On-chip stacks preserve the processor status and are automati-
cally maintained during interrupt handling. The stacks are twelve
levels deep to allow interrupt, loop and subroutine nesting.
The following instructions allow global enable or disable servic-
ing of the interrupts (including power-down), regardless of the
state of IMASK. Disabling the interrupts does not affect serial
port autobuffering or DMA.
ENA INTS;
DIS INTS;
When the processor is reset, interrupt servicing is enabled.
LOW POWER OPERATION
The ADSP-2184L has three low power modes that significantly
reduce the power dissipation when the device operates under
standby conditions. These modes are:
• Power-Down
• Idle
• Slow Idle
The CLKOUT pin may also be disabled to reduce external
power dissipation.
Power-Down
The ADSP-2184L processor has a low power feature that lets
the processor enter a very low power dormant state through
hardware or software control. Following is a brief list of power-
down features. Refer to the ADSP-2100 Family User’s Manual,
Third Edition, “System Interface” chapter, for detailed informa-
tion about the power-down feature.
• Quick recovery from power-down. The processor begins
executing instructions in as few as 400 CLKIN cycles.
• Support for an externally generated TTL or CMOS proces-
sor clock. The external clock can continue running during
power-down without affecting the lowest power rating and
400 CLKIN cycle recovery.
• Support for crystal operation includes disabling the oscillator
to save power (the processor automatically waits approxi-
mately 4096 CLKIN cycles for the crystal oscillator to start
or stabilize), and letting the oscillator run to allow 400 CLKIN
cycle start-up.
• Power-down is initiated by either the power-down pin (PWD)
or the software power-down force bit.
• Interrupt support allows an unlimited number of instructions
to be executed before optionally powering down. The power-
down interrupt also can be used as a nonmaskable, edge-
sensitive interrupt.
• Context clear/save control allows the processor to continue
where it left off or start with a clean context when leaving the
power-down state.
• The RESET pin also can be used to terminate power-down.
• Power-down acknowledge (PWDACK) pin indicates when
the processor has entered power-down.
REV. 0
–5–
5 Page 
ADSP-2184L
Flag I/O Pins
The ADSP-2184L has eight general purpose programmable input/
output flag pins. They are controlled by two memory mapped
registers. The PFTYPE register determines the direction,
1 = output and 0 = input. The PFDATA register is used to read
and write the values on the pins. Data being read from a pin
configured as an input is synchronized to the ADSP-2184L’s
clock. Bits that are programmed as outputs will read the value
being output. The PF pins default to input during reset.
In addition to the programmable flags, the ADSP-2184L has
five fixed-mode flags, FLAG_IN, FLAG_OUT, FL0, FL1 and
FL2. FL0-FL2 are dedicated output flags. FLAG_IN and
FLAG_OUT are available as an alternate configuration of
SPORT1.
Note: Pins PF0, PF1 and PF2 are also used for device configu-
ration during reset.
INSTRUCTION SET DESCRIPTION
The ADSP-2184L assembly language instruction set has an
algebraic syntax that was designed for ease of coding and
readability. The assembly language, which takes full advantage
of the processor’s unique architecture, offers the following benefits:
• The algebraic syntax eliminates the need to remember cryptic
assembler mnemonics. For example, a typical arithmetic add
instruction, such as AR = AX0 + AY0, resembles a simple
equation.
• Every instruction assembles into a single, 24-bit word that
can execute in a single instruction cycle.
• The syntax is a superset ADSP-2100 Family assembly lan-
guage and is completely source and object code compatible
with other family members. Programs may need to be relo-
cated to utilize on-chip memory and conform to the ADSP-
2184L’s interrupt vector and reset vector map.
• Sixteen condition codes are available. For conditional jump,
call, return or arithmetic instructions, the condition can be
checked and the operation executed in the same instruction
cycle.
• Multifunction instructions allow parallel execution of an
arithmetic instruction with up to two fetches or one write to
processor memory space during a single instruction cycle.
DESIGNING AN EZ-ICE-COMPATIBLE SYSTEM
The ADSP-2184L has on-chip emulation support and an
ICE-Port, a special set of pins that interface to the EZ-ICE. These
features allow in-circuit emulation without replacing the target
system processor by using only a 14-pin connection from the
target system to the EZ-ICE. Target systems must have a 14-pin
connector to accept the EZ-ICE’s in-circuit probe, a 14-pin plug.
Issuing the chip reset command during emulation causes the
DSP to perform a full chip reset, including a reset of its memory
mode. Therefore, it is vital that the mode pins are set correctly
PRIOR to issuing a chip reset command from the emulator user
interface.
If using a passive method of maintaining mode information (as
discussed in Setting Memory Modes), it does not matter that
the mode information is latched by an emulator reset. However,
if using the RESET pin as a method of setting the value of the
mode pins, the effects of an emulator reset must be taken into
consideration.
One method of ensuring that the values located on the mode
pins are the desired values is to construct a circuit like the one
shown in Figure 7. This circuit forces the value located on the
Mode A pin to logic low, regardless if it latched via the RESET
or ERESET pin.
ERESET
RESET
ADSP-2184L
1k⍀
MODE A/PF0
PROGRAMMABLE I/O
Figure 7. Boot Mode Circuit
See the ADSP-2100 Family EZ-Tools data sheet for complete
information on ICE products.
The ICE-Port interface consists of the following ADSP-2184L
pins:
EBR
EMS
EBG
EINT
ERESET
ECLK
ELIN
ELOUT EE
These ADSP-2184L pins are usually connected only to the
EZ-ICE connector in the target system. These pins have no
function except during emulation, and do not require pull-up
or pull-down resistors. The traces for these signals between
the ADSP-2184L and the connector must be kept as short as
possible, no longer than three inches.
The following pins are also used by the EZ-ICE:
BR BG
RESET GND
The EZ-ICE uses the EE (emulator enable) signal to take con-
trol of the ADSP-2184L in the target system. This causes the
processor to use its ERESET, EBR and EBG pins instead of
the RESET, BR and BG pins. The BG output is three-stated.
These signals do not need to be jumper-isolated in your system.
The EZ-ICE connects to your target system via a ribbon cable
and a 14-pin female plug. The female plug is plugged onto the
14-pin connector (a pin strip header) on the target board.
REV. 0
–11–
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