ADSP-2171 Datasheet PDF - Analog Devices
| Part Number | ADSP-2171 | |
| Description | ADSP-2100 Family DSP Microcomputers | |
| Manufacturers | Analog Devices | |
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a
DSP Microcomputer
ADSP-2171/ADSP-2172/ADSP-2173
FEATURES
30 ns Instruction Cycle Time (33 MIPS) from
16.67 MHz Crystal at 5.0 V
50 ns Instruction Cycle Time (20 MIPS) from 10 MHz
Crystal at 3.3 V
ADSP-2100 Family Code & Function Compatible with
New Instruction Set Enhancements for Bit Manipula-
tion Instructions, Multiplication Instructions, Biased
Rounding, and Global Interrupt Masking
Bus Grant Hang Logic
2K Words of On-Chip Program Memory RAM
2K Words of On-Chip Data Memory RAM
8K Words of On-Chip Program Memory ROM
(ADSP-2172)
8- or 16-Bit Parallel Host Interface Port
300 mW Typical Power Dissipation at 5.0 V at 30 ns
70 mW Typical Power Dissipation at 3.3 V at 50 ns
Powerdown Mode Featuring Less than 0.55 mW (ADSP-
2171/ADSP-2172) or 0.36 mW (ADSP-2173) CMOS
Standby Power Dissipation with 100 Cycle Recovery
from Powerdown
Dual Purpose Program Memory for Both Instruction
and Data Storage
Independent ALU, Multiplier/Accumulator, and Barrel
Shifter Computational Units
Two Independent Data Address Generators
Powerful Program Sequencer Provides
Zero Overhead Looping
Conditional Instruction Execution
Two Double-Buffered Serial Ports with Companding
Hardware and Automatic Data Buffering
Programmable 16-Bit Interval Timer with Prescaler
Programmable Wait State Generation
Automatic Booting of Internal Program Memory from
Byte-Wide External Memory, e.g., EPROM, or
Through Host Interface Port
Stand-Alone ROM Execution (Optional)
Single-Cycle Instruction Execution
Single-Cycle Context Switch
Multifunction Instructions
Three Edge- or Level-Sensitive External Interrupts
Low Power Dissipation in Standby Mode
128-Lead TQFP and 128-Lead PQFP
GENERAL DESCRIPTION
The ADSP-2171, ADSP-2172, and ADSP-2173 are single-chip
microcomputers optimized for digital signal processing (DSP)
and other high-speed numeric processing applications. The
ADSP-2171 and ADSP-2172 are designed for 5.0 V applica-
tions. The ADSP-2173 is designed for 3.3 V applications. The
ADSP-2172 also has 8K words (24-bit) of program ROM.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
FUNCTIONAL BLOCK DIAGRAM
DATA
ADDRESS
GENERATORS
DAG 1 DAG 2
PROGRAM
SEQUENCER
PROGRAM
ROM
8K x 24
PROGRAM
RAM
2K x 24
MEMORY
DATA
MEMORY
2K x 16
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
POWERDOWN
CONTROL
LOGIC
FLAGS
EXTERNAL
ADDRESS
BUS
PROGRAM MEMORY DATA
DATA MEMORY DATA
ARITHMETIC UNITS
ALU MAC SHIFTER
ADSP-2100 BASE
ARCHITECTURE
SERIAL PORTS
SPORT 0 SPORT 1
TIMER
EXTERNAL
DATA
BUS
HOST
INTERFACE
PORT
The ADSP-217x combines the ADSP-2100 base architecture
(three computational units, data address generators, and a pro-
gram sequencer) with two serial ports, a host interface port, a
programmable timer, extensive interrupt capabilities, and on-
chip program and data memory.
In addition, the ADSP-217x supports new instructions, which
include bit manipulations–bit set, bit clear, bit toggle, bit test–
new ALU constants, new multiplication instruction (x squared),
biased rounding, and global interrupt masking, for increased
flexibility. The ADSP-217x also has a Bus Grant Hang Logic
(BGH) feature.
The ADSP-217x provides 2K words (24-bit) of program RAM
and 2K words (16-bit) of data memory. The ADSP-2172 pro-
vides an additional 8K words (24-bit) of program ROM. Power-
down circuitry is also provided to meet the low power needs of
battery operated portable equipment. The ADSP-217x is avail-
able in 128-pin TQFP and 128-pin PQFP packages.
Fabricated in a high-speed, double metal, low power, CMOS
process, the ADSP-217X operates with a 30 ns instruction cycle
time. Every instruction can execute in a single processor cycle.
The ADSP-217x’s flexible architecture and comprehensive in-
struction set allow the processor to perform multiple operations
in parallel. In one processor cycle the ADSP-217x can:
• generate the next program address
• fetch the next instruction
• perform one or two data moves
• update one or two data address pointers
• perform a computational operation
This takes place while the processor continues to:
• receive and transmit data through the two serial ports
• receive and/or transmit data through the host interface port
• decrement timer
© Analog Devices, Inc., 1995
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
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ADSP-2171/ADSP-2172/ADSP-2173
Interrupts
The interrupt controller allows the processor to respond to the
eleven possible interrupts and reset with minimum overhead.
The ADSP-217x provides up to three external interrupt input
pins, IRQ0, IRQ1 and IRQ2. IRQ2 is always available as a dedi-
cated pin; SPORT1 may be reconfigured for IRQ0, IRQ1, and
the flags. The ADSP-217x also supports internal interrupts from
the timer, the host interface port, the two serial ports, software,
and the powerdown control circuit. The interrupt levels are in-
ternally prioritized and individually maskable (except power-
down and reset). The input pins can be programmed to be
either level- or edge-sensitive. The priorities and vector ad-
dresses of all interrupts are shown in Table II, and the interrupt
registers are shown in Figure 2.
Interrupts can be masked or unmasked with the IMASK regis-
ter. Individual interrupt requests are logically ANDed with the
bits in IMASK; the highest priority unmasked interrupt is then
selected.The powerdown interrupt is nonmaskable.
The ADSP-217x masks all interrupts for one instruction cycle
following the execution of an instruction that modifies the
IMASK register. This does not affect autobuffering.
The interrupt control register, ICNTL, allows the external in-
terrupts to be either edge- or level-sensitive. Interrupt routines
can either be nested with higher priority interrupts taking prece-
dence or processed sequentially.
The IFC register is a write-only register used to force and clear
interrupts generated from software.
Table II. Interrupt Priority & Interrupt Vector Addresses
Source of Interrupt
Interrupt Vector
Address (Hex)
Reset (or Power-Up with PUCR = 1)
Powerdown (Nonmaskable)
IRQ2
HIP Write
HIP Read
SPORT0 Transmit
SPORT0 Receive
Software Interrupt 1
Software Interrupt 0
SPORT1 Transmit or IRQ1
SPORT1 Receive or IRQ0
Timer
0000 (Highest Priority)
002C
0004
0008
000C
0010
0014
0018
001C
0020
0024
0028 (Lowest Priority)
On-chip stacks preserve the processor status and are automati-
cally maintained during interrupt handling.
The stacks are twelve levels deep to allow interrupt nesting.
The following instructions allow global enable or disable servic-
ing of the interrupts (including powerdown), regardless of the
state of IMASK. Disabling the interrupts does not affect
autobuffering.
ENA INTS;
DIS INTS;
When you reset the processor, the interrupt servicing is enabled.
ICNTL
43210
0
IMASK
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 = enable, 0 = disable
IRQ0 Sensitivity
IRQ1 Sensitivity
IRQ2 Sensitivity
1 = edge
0 = level
Interrupt Nesting
1 = enable, 0 = disable
IRQ2
HIP Write
HIP Read
SPORT0 Transmit
SPORT0 Receive
IFC
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 000 0 0 0 0 0 0 0 0 0 0
Timer
IRQ0 or SPORT1 Receive
IRQ1 or SPORT1 Transmit
Software 0
Software 1
INTERRUPT FORCE
IRQ2
SPORT0 Transmit
SPORT0 Receive
Software 1
Software 0
SPORT1 Transmit or IRQ1
SPORT1 Receive or IRQ0
Timer
INTERRUPT CLEAR
Timer
SPORT1 Receive or IRQ0
SPORT1 Transmit or IRQ1
Software 0
Software 1
SPORT0 Receive
SPORT0 Transmit
IRQ2
Figure 2. Interrupt Registers
REV. A
–5–
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Featured Datasheets
| Part Number | Description | MFRS |
| ADSP-2171 | The function is DSP Microcomputer. Analog Devices | |
| ADSP-2171 | The function is ADSP-2100 Family DSP Microcomputers. Analog Devices | |
| ADSP-2171 | The function is ADSP-2100 Family DSP Microcomputers. Analog Devices | |
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