ADSP-2164 Datasheet PDF - Analog Devices
| Part Number | ADSP-2164 | |
| Description | ADSP-2100 Family DSP Microcomputers | |
| Manufacturers | Analog Devices | |
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DSP Microcomputers with ROM
ADSP-216x
SUMMARY
16-Bit Fixed-Point DSP Microprocessors with
On-Chip Memory
Enhanced Harvard Architecture for Three-Bus
Performance: Instruction Bus and Dual Data Buses
Independent Computation Units: ALU, Multiplier/
Accumulator and Shifter
Single-Cycle Instruction Execution and Multifunction
Instructions
On-Chip Program Memory ROM and Data Memory RAM
Integrated I/O Peripherals: Serial Ports, Timer
FEATURES
25 MIPS, 40 ns Maximum Instruction Rate (5 V)
Separate On-Chip Buses for Program and Data Memory
Program Memory Stores Both Instructions and Data
(Three-Bus Performance)
Dual Data Address Generators with Modulo and
Bit-Reverse Addressing
Efficient Program Sequencing with Zero-Overhead
Looping: Single-Cycle Loop Setup
Double-Buffered Serial Ports with Companding Hardware,
Automatic Data Buffering and Multichannel Operation
Three Edge- or Level-Sensitive Interrupts
Low Power IDLE Instruction
PLCC and MQFP Packages
GENERAL DESCRIPTION
The ADSP-216x Family processors are single-chip micro-
computers␣ optimized␣ for␣ digital␣ signal␣ processing␣ (DSP)
and other high speed numeric processing applications. The
ADSP-216x processors are all built upon a common core with
ADSP-2100. Each processor combines the core DSP architec-
ture—computation units, data address generators and program
sequencer—with features such as␣ on-chip program ROM and
data memory RAM, a programmable timer and two serial ports.
The ADSP-2165/ADSP-2166 also adds program memory and
power-down mode.
This data sheet describes the following ADSP-216x Family
processors:
ADSP-2161/ADSP-2162/
ADSP-2163/ADSP-2164
ADSP-2165/ADSP-2166
Custom ROM-programmed DSPs:
ROM-programmed ADSP-216x
processors with power-down and
larger on-chip memories (12K Pro-
gram Memory ROM, 1K Program
Memory RAM, 4K Data Memory
RAM)
FUNCTIONAL BLOCK DIAGRAM
DATA ADDRESS
GENERATORS PROGRAM
SEQUENCER
DAG 1 DAG 2
MEMORY
PROGRAM
MEMORY
DATA
MEMORY
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
ARITHMETIC UNITS
ALU MAC SHIFTER
ADSP-2100 CORE
SERIAL PORTS
SPORT 0 SPORT 1
TIMER
EXTERNAL
ADDRESS
BUS
EXTERNAL
DATA
BUS
Fabricated in a high speed, submicron, double-layer metal
CMOS process, the highest-performance ADSP-216x proces-
sors operate at 25 MHz with a 40 ns instruction cycle time.
Every instruction can execute in a single cycle. Fabrication in
CMOS results in low power dissipation.
The ADSP-2100 Family’s flexible architecture and compre-
hensive instruction set support a high degree of parallelism.
In one cycle the ADSP-216x can␣ perform␣ all of␣ the␣ following
operations:
•␣ Generate the next program address
•␣ Fetch the next instruction
•␣ Perform one or two data moves
•␣ Update one or two data address pointers
•␣ Perform a computation
•␣ Receive and transmit data via one or two serial ports
Table I shows the features of each ADSP-216x processor.
The ADSP-216x series are memory-variant versions of the
ADSP-2101 and ADSP-2103 that contain factory-programmed
on-chip ROM program memory. These devices offer different
amounts of on-chip memory for program and data storage.
Table I shows the features available in the ADSP-216x series of
custom ROM-coded processors.
The ADSP-216x products eliminate the need for an external
boot EPROM in your system, and can also eliminate the need
for any external program memory by fitting the entire applica-
tion program in on-chip ROM. These devices thus provide an
excellent option for volume applications where board space and
system cost constraints are of critical concern.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
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ADSP-216x
The ADSP-216x serial ports offer the following capabilities:
Bidirectional—Each SPORT has a separate, double-buffered
transmit and receive function.
Flexible Clocking—Each SPORT can use an external serial
clock or generate its own clock internally.
Flexible Framing—The SPORTs have independent framing
for the transmit and receive functions; each function can run in
a frameless mode or with frame synchronization signals inter-
nally generated or externally generated; frame sync signals may
be active high or inverted, with either of two pulsewidths and
timings.
Different Word Lengths—Each SPORT supports serial data
word lengths from 3 to 16 bits.
Companding in Hardware—Each SPORT provides optional
A-law and µ-law companding according to CCITT recommen-
dation G.711.
Flexible Interrupt Scheme—Receive and transmit functions
can generate a unique interrupt upon completion of a data word
transfer.
Autobuffering with Single-Cycle Overhead—Each SPORT
can automatically receive or transmit the contents of an entire
circular data buffer with only one overhead cycle per data word;
an interrupt is generated after the transfer of the entire buffer is
completed.
Multichannel Capability (SPORT0 Only)—SPORT0 pro-
vides a multichannel interface to selectively receive or transmit a
24-word or 32-word, time-division multiplexed serial bit stream;
this feature is especially useful for T1 or CEPT interfaces, or as
a network communication scheme for multiple processors.
Alternate Configuration—SPORT1 can be alternatively
configured as two external interrupt inputs (IRQ0, IRQ1) and
the Flag In and Flag Out signals (FI, FO).
Interrupts
The ADSP-216x’s interrupt controller lets the processor re-
spond to interrupts with a minimum of overhead. Up to three
external interrupt input pins, IRQ0, IRQ1 and IRQ2, are pro-
vided. IRQ2 is always available as a dedicated pin; IRQ1 and
IRQ0 may be alternately configured as part of Serial Port 1. The
ADSP-216x also supports internal interrupts from the timer and
the serial ports. The interrupts are internally prioritized and
individually maskable (except for RESET which is nonmaskable).
The IRQx input pins can be programmed for either level- or
edge-sensitivity. The interrupt priorities for each ADSP-216x
processor are shown in Table II.
Table II.␣ Interrupt Vector Addresses and Priority
ADSP-216x Interrupt Source
RESET Startup
IRQ2 or Power-Down
SPORT0 Transmit
SPORT0 Receive
SPORT1 Transmit or IRQ1
SPORT1 Receive or IRQ0
Timer
Interrupt
Vector Address
0x0000
0x0004 (High Priority)
0x0008
0x000C
0x0010
0x0014
0x0018 (Low Priority)
The ADSP-216x uses a vectored interrupt scheme: when an
interrupt is acknowledged, the processor shifts program control
to the interrupt vector address corresponding to the interrupt
received. Interrupts can be optionally nested so that a higher
priority interrupt can preempt the currently executing interrupt
service routine. Each interrupt vector location is four instruc-
tions in length so that simple service routines can be coded
entirely in this space. Longer service routines require an addi-
tional JUMP or CALL instruction.
Individual interrupt requests are logically ANDed with the bits
in the IMASK register; the highest-priority unmasked interrupt
is then selected.
The interrupt control register, ICNTL, allows the external
interrupts to be set as either edge- or level-sensitive. Depending
on Bit 4 in ICNTL, interrupt service routines can either be
nested (with higher priority interrupts taking precedence) or be
processed sequentially (with only one interrupt service active at
a time).
The interrupt force and clear register, IFC, is a write-only regis-
ter that contains a force bit and a clear bit for each interrupt.
When responding to an interrupt, the ASTAT, MSTAT and
IMASK status registers are pushed onto the status stack and
the PC counter is loaded with the appropriate vector address.
The status stack is seven levels deep to allow interrupt nesting.
The stack is automatically popped when a return from the inter-
rupt instruction is executed.
Pin Definitions
Pin Function Descriptions show pin definitions for the ADSP-
216x processors. Any inputs not used must be tied to VDD.
SYSTEM INTERFACE
Figure 3 shows a typical system for the ADSP-216x with two
serial I/O devices, an optional external program and data
memory. A total of 12K words of data memory and 15K words
of program memory is addressable.
Programmable wait-state generation allows the processors to
easily interface to slow external memories.
The ADSP-216x processors also provide either: one external
interrupt (IRQ2) and two serial ports (SPORT0, SPORT1), or
three external interrupts (IRQ2, IRQ1, IRQ0) and one serial
port (SPORT0).
Clock Signals
The ADSP-216x processors’ CLKIN input may be driven by a
crystal or by a TTL-compatible external clock signal. The
CLKIN input may not be halted or changed in frequency during
operation, nor operated below the specified low frequency limit.
If an external clock is used, it should be a TTL-compatible
signal running at the instruction rate. The signal should be
connected to the processor’s CLKIN input; in this case, the
XTAL input must be left unconnected.
Because the ADSP-216x processors include an on-chip oscilla-
tor circuit, an external crystal may also be used. The crystal
should be connected across the CLKIN and XTAL pins, with
two capacitors connected as shown in Figure 2. A parallel-
resonant, fundamental frequency, microprocessor-grade crystal
should be used.
REV. 0
–5–
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