ADSP-2100AJG Datasheet PDF - Analog Devices
| Part Number | ADSP-2100AJG | |
| Description | 12.5 MIPS DSP Microprocessor | |
| Manufacturers | Analog Devices | |
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ADSP-2100 Family
DSP Microcomputers
ADSP-21xx
SUMMARY
16-Bit Fixed-Point DSP Microprocessors with
On-Chip Memory
Enhanced Harvard Architecture for Three-Bus
Performance: Instruction Bus & Dual Data Buses
Independent Computation Units: ALU, Multiplier/
Accumulator, and Shifter
Single-Cycle Instruction Execution & Multifunction
Instructions
On-Chip Program Memory RAM or ROM
& Data Memory RAM
Integrated I/O Peripherals: Serial Ports, Timer,
Host Interface Port (ADSP-2111 Only)
FEATURES
25 MIPS, 40 ns Maximum Instruction Rate
Separate On-Chip Buses for Program and Data Memory
Program Memory Stores Both Instructions and Data
(Three-Bus Performance)
Dual Data Address Generators with Modulo and
Bit-Reverse Addressing
Efficient Program Sequencing with Zero-Overhead
Looping: Single-Cycle Loop Setup
Automatic Booting of On-Chip Program Memory from
Byte-Wide External Memory (e.g., EPROM )
Double-Buffered Serial Ports with Companding Hardware,
Automatic Data Buffering, and Multichannel Operation
ADSP-2111 Host Interface Port Provides Easy Interface
to 68000, 80C51, ADSP-21xx, Etc.
Automatic Booting of ADSP-2111 Program Memory
Through Host Interface Port
Three Edge- or Level-Sensitive Interrupts
Low Power IDLE Instruction
PGA, PLCC, PQFP, and TQFP Packages
MIL-STD-883B Versions Available
GENERAL DESCRIPTION
The ADSP-2100 Family processors are single-chip micro-
computers optimized for digital signal processing (DSP)
and other high speed numeric processing applications. The
ADSP-21xx processors are all built upon a common core. Each
processor combines the core DSP architecture—computation
units, data address generators, and program sequencer—with
differentiating features such as on-chip program and data
memory RAM, a programmable timer, one or two serial ports,
and, on the ADSP-2111, a host interface port.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
FUNCTIONAL BLOCK DIAGRAM
DATA ADDRESS
GENERATORS
DAG 1 DAG 2
PROGRAM
SEQUENCER
MEMORY
PROGRAM
MEMORY
DATA
MEMORY
PROGRAM MEMORY ADDRESS
FLAGS
(ADSP-2111)
EXTERNAL
ADDRESS
BUS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
ARITHMETIC UNITS
ALU MAC SHIFTER
ADSP-2100 CORE
SERIAL PORTS
SPORT 0 SPORT 1
TIMER
EXTERNAL
DATA
HOST
BUS
INTERFACE
PORT
(ADSP-2111)
This data sheet describes the following ADSP-2100 Family
processors:
ADSP-2101
ADSP-2103
ADSP-2105
ADSP-2111
ADSP-2115
ADSP-2161/62/63/64
3.3 V Version of ADSP-2101
Low Cost DSP
DSP with Host Interface Port
Custom ROM-programmed DSPs
The following ADSP-2100 Family processors are not included
in this data sheet:
ADSP-2100A
DSP Microprocessor
ADSP-2165/66
ROM-programmed ADSP-216x processors
with powerdown and larger on-chip
memories (12K Program Memory ROM,
1K Program Memory RAM, 4K Data
Memory RAM)
ADSP-21msp5x
Mixed-Signal DSP Processors with
integrated on-chip A/D and D/A plus
powerdown
ADSP-2171
Speed and feature enhanced ADSP-2100
Family processor with host interface port,
powerdown, and instruction set extensions
for bit manipulation, multiplication, biased
rounding, and global interrupt masking
ADSP-2181
ADSP-21xx processor with ADSP-2171
features plus 80K bytes of on-chip RAM
configured as 16K words of program
memory and 16K words of data memory.
Refer to the individual data sheet of each of these processors for
further information.
© Analog Devices, Inc., 1996
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
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ADSP-21xx
DATA
ADDRESS
GENERATOR
#1
DATA
ADDRESS
GENERATOR
#2
14 PMA BUS
14 DMA BUS
24 PMD BUS
16 DMD BUS
INSTRUCTION
REGISTER
PROGRAM
SEQUENCER
PROGRAM
MEMORY
SRAM
or ROM
DATA
MEMORY
SRAM
BOOT
ADDRESS
GENERATOR
FLAGS
(ADSP-2111 Only)
TIMER
3
24 16 PMA BUS
DMA BUS
14
MUX
EXTERNAL
ADDRESS
BUS
BUS
EXCHANGE
PMD BUS
DMD BUS
24 EXTERNAL
MUX
DATA
BUS
INPUT REGS
ALU
OUTPUT REGS
INPUT REGS
MAC
OUTPUT REGS
INPUT REGS
SHIFTER
OUTPUT REGS
16
R Bus
COMPANDING
CIRCUITRY
TRANSMIT REG
RECEIVE REG
SERIAL
PORT 0
(Not on ADSP-2105)
TRANSMIT REG
RECEIVE REG
SERIAL
PORT 1
55
Figure 1. ADSP-21xx Block Diagram
HOST
PORT
CONTROL
HOST
PORT
DATA
11
EXTERNAL
HOST PORT
BUS
16
HOST INTERFACE PORT
(ADSP-2111 Only)
One bus grant execution mode (GO Mode) allows the ADSP-
21xx to continue running from internal memory. A second
execution mode requires the processor to halt while buses are
granted.
Each ADSP-21xx processor can respond to several different
interrupts. There can be up to three external interrupts,
configured as edge- or level-sensitive. Internal interrupts can be
generated by the timer, serial ports, and, on the ADSP-2111,
the host interface port. There is also a master RESET signal.
Booting circuitry provides for loading on-chip program memory
automatically from byte-wide external memory. After reset,
three wait states are automatically generated. This allows, for
example, a 60 ns ADSP-2101 to use a 200 ns EPROM as
external boot memory. Multiple programs can be selected and
loaded from the EPROM with no additional hardware.
The data receive and transmit pins on SPORT1 (Serial Port 1)
can be alternatively configured as a general-purpose input flag
and output flag. You can use these pins for event signalling to
and from an external device. The ADSP-2111 has three
additional flag outputs whose states are controlled through
software.
A programmable interval timer can generate periodic interrupts.
A 16-bit count register (TCOUNT) is decremented every n
cycles, where n–1 is a scaling value stored in an 8-bit register
(TSCALE). When the value of the count register reaches zero,
an interrupt is generated and the count register is reloaded from
a 16-bit period register (TPERIOD).
Serial Ports
The ADSP-21xx processors include two synchronous serial
ports (“SPORTs”) for serial communications and multiproces-
sor communication. All of the ADSP-21xx processors have two
serial ports (SPORT0, SPORT1) except for the ADSP-2105,
which has only SPORT1.
The serial ports provide a complete synchronous serial interface
with optional companding in hardware. A wide variety of
framed or frameless data transmit and receive modes of opera-
tion are available. Each SPORT can generate an internal
programmable serial clock or accept an external serial clock.
Each serial port has a 5-pin interface consisting of the following
signals:
Signal Name
SCLK
RFS
TFS
DR
DT
Function
Serial Clock (I/O)
Receive Frame Synchronization (I/O)
Transmit Frame Synchronization (I/O)
Serial Data Receive
Serial Data Transmit
The ADSP-21xx serial ports offer the following capabilities:
Bidirectional—Each SPORT has a separate, double-buffered
transmit and receive function.
Flexible Clocking—Each SPORT can use an external serial
clock or generate its own clock internally.
REV. B
–5–
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