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PDF ADS930 Data sheet ( Hoja de datos )
| Número de pieza | ADS930 | |
| Descripción | 8-Bit/ 30MHz Sampling ANALOG-TO-DIGITAL CONVERTER | |
| Fabricantes | Burr-Brown Corporation | |
| Logotipo |  |
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®
ADS930E
ADS930
8-Bit, 30MHz Sampling
TM
ANALOG-TO-DIGITAL CONVERTER
FEATURES
q +3V TO +5V SUPPLY OPERATION
q INTERNAL REFERENCE
q SINGLE-ENDED INPUT RANGE: 1V to 2V
q LOW POWER: 66mW at +3V
q HIGH SNR: 46dB
q LOW DNL: 0.4LSB
q 28-LEAD SSOP PACKAGE
APPLICATIONS
q BATTERY POWERED EQUIPMENT
q CAMCORDERS
q PORTABLE TEST EQUIPMENT
q COMPUTER SCANNERS
q COMMUNICATIONS
ADS930
DESCRIPTION
The ADS930 is a high speed pipelined analog-to-
digital converter specified to operate from nominal
+3V or +5V power supplies with tolerances of up to
10%. This complete converter includes a high band-
width track/hold, a 8-bit quantizer and an internal
reference.
The ADS930 employs digital error correction tech-
niques to provide excellent differential linearity for
demanding imaging applications. Its low distortion
and high SNR give the extra margin needed for
telecommunications, video and test instrumentation
applications.
This high performance A/D converter is specified for
performance at a 30MHz sampling rate. The ADS930
is available in a 28-lead SSOP package.
CLK
Timing
Circuitry
LVDD
2V
IN
1V
IN
(Opt.)
T/H
Pipeline
A/D
Error
Correction
3-State
Outputs
8-Bit
Digital
Data
Internal
Reference
LpBy CM LnBy
1VREF Pwrdn OE
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
©1997 Burr-Brown Corporation
PDS-1348B
Printed in U.S.A. March, 1997
1 page  
TYPICAL PERFORMANCE CURVES
At TA = +25°C, VS = +3V, Single-ended Input and Sampling Rate = 30MHz, unless otherwise specified.
0
–20
–40
–60
–80
–100
0
SPECTRAL PERFORMANCE
fIN = 500kHz
5 10
Frequency (MHz)
15
0
–20
–40
–60
–80
–100
0
SPECTRAL PERFORMANCE
fIN = 3.58MHz
5 10
Frequency (MHz)
15
0
–20
–40
–60
–80
–100
0
SPECTRAL PERFORMANCE
fIN = 12MHz
5 10
Frequency (MHz)
15
0
–20
–40
–60
–80
–100
0
TWO-TONE INTERMODULATION
f1 = 3.5MHz at –7dBFS
f2 = 3.4MHz at –7dBFS
2f1 –f2 = 54.7dBFS
2f2 –f1 = 54.2dBFS
2468
Frequency (MHz)
10
2.0
1.0
0.0
–1.0
–2.0
0
DIFFERENTIAL LINEARITY ERROR
fIN = 500kHz
64 128 192
Output Code
256
2.0
1.0
0.0
–1.0
–2.0
0
DIFFERENTIAL LINEARITY ERROR
fIN = 12MHz
64 128 192
Output Code
256
®
5 ADS930
5 Page 
recommended to meet the rated performance specifications.
However, the ADS930 performance is tolerant to duty cycle
variations of as much as ±10%, which should not affect the
performance. For applications operating with input frequen-
cies up to Nyquist (fCLK/2) or undersampling applications,
special considerations must be made to provide a clock with
very low jitter. Clock jitter leads to aperture jitter (tA) which
can be the ultimate limitation in achieving good SNR perfor-
mance. Equation (4) shows the relationship between aper-
ture jitter, input frequency and the signal-to-noise ratio:
SNR = 20log10 [1/(2 π fIN tA)]
(4)
SINGLE-ENDED INPUT
(IN = 1.5V DC)
+FS (IN = +2V)
+FS –1LSB
+FS –2LSB
+3/4 Full Scale
+1/2 Full Scale
+1/4 Full Scale
+1LSB
Bipolar Zero (IN +1.5V)
–1LSB
–1/4 Full Scale
–1/2 Full Scale
–3/4 Full Scale
–FS +1LSB
–FS (IN = +1V)
STRAIGHT OFFSET BINARY
(SOB)
PIN 12
FLOATING or LO
11111111
11111111
11111110
11100000
11000000
10100000
10000001
10000000
01111111
01100000
01000000
00100000
00000001
00000000
TABLE I. Coding Table for the ADS930.
DIGITAL OUTPUTS
There is a 5.0 clock cycle data latency from the start convert
signal to the valid output data. The standard output coding
is Straight Offset Binary where a full scale input signal
corresponds to all “1’s” at the output. The digital outputs of
the ADS930 can be set to a high impedance state by driving
the OE (pin 16) with a logic “HI”. Normal operation is
achieved with pin 16 “LO” or Floating due to internal pull-
down resistors. This function is provided for testability
purposes but is not recommended to be used dynamically.
The digital outputs of the ADS930 are standard CMOS
stages and designed to be compatible to both high speed
TTL and CMOS logic families. The logic thresholds are for
low-voltage CMOS: VOL = 0.4V, VOH = 2.4V, which allows
the ADS930 to directly interface to 3V-logic. The digital
output driver of the ADS930 uses a dedicated digital supply
pin (pin 2, LVDD) see Figure 7. By adjusting the voltage on
LVDD, the digital output levels will vary respectively. It is
recommended to limit the fan-out to one in order to keep the
capacitive loading on the data lines below the specified
15pF. If necessary, external buffers or latches may be used
to provide the added benefit of isolating the A/D converter
from any digital activities on the bus coupling back high
frequency noise which degrades the performance.
POWER-DOWN MODE
The ADS930’s low power consumption can be reduced even
further by initiating a power-down mode. For this, the Power
Down Pin (Pin 17) must be tied to a logic “High” reducing
the current drawn from the supply by approximately 70%. In
normal operation, the power-down mode is disabled by an
internal pull-down resistor (50kΩ).
During power-down, the digital outputs are set in 3-state.
With the clock applied, the converter does not accurately
process the sampled signal. After removing the power-down
condition, the output data from the following 5 clock cycles
is invalid (data latency).
DECOUPLING AND GROUNDING
CONSIDERATIONS
The ADS930 has several supply pins, one of which is
dedicated to supply only the output driver (LVDD). The
remaining supply pins are not divided into analog and digital
supply pins since they are internally connected on the chip.
For this reason, it is recommended that the converter be
treated as an analog component and to power it from the
analog supply only. Digital supply lines often carry high
levels of noise which can couple back into the converter and
limit performance.
Because of the pipeline architecture, the converter also
generates high frequency transients and noise that are fed
back into the supply and reference lines. This requires that
the supply and reference pins be sufficiently bypassed.
Figure 8 shows the recommended decoupling scheme for the
analog supplies. In most cases 0.1µF ceramic chip capacitors
are adequate to keep the impedance low over a wide fre-
quency range. Their effectiveness largely depends on the
proximity to the individual supply pin. Therefore, they
should be located as close as possible to the supply pins.
ADS930
VS GND
1 13 14
VS
18
GND
19 20
VS
28
+VS +LVDD
ADS930
Digital
Output
Stage
0.1µF
0.1µF
0.1µF
FIGURE 8. Recommended Bypassing for Analog Supply
Pins.
FIGURE 7. Independent Supply Connection for Output
Stage.
11
ADS930
®
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet ADS930.PDF ] | |
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