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PDF ADS8344 Data sheet ( Hoja de datos )
| Número de pieza | ADS8344 | |
| Descripción | 16-Bit/ 8-Channel Serial Output Sampling ANALOG-TO-DIGITAL CONVERTER | |
| Fabricantes | Burr-Brown Corporation | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ADS8344 (archivo pdf) en la parte inferior de esta página. Total 13 Páginas | ||
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®
ADS8344 ¤
ADS8344
For most current data sheet and other product
information, visit www.burr-brown.com
ADS8344 ¤
16-Bit, 8-Channel Serial Output Sampling
ANALOG-TO-DIGITAL CONVERTER
FEATURES
q PIN FOR PIN WITH ADS7844
q SINGLE SUPPLY: 2.7V to 5V
q 8-CHANNEL SINGLE-ENDED OR
4-CHANNEL DIFFERENTIAL INPUT
q UP TO 100kHz CONVERSION RATE
q 84dB SINAD
q SERIAL INTERFACE
q QSOP-20 AND SSOP-20 PACKAGES
APPLICATIONS
q DATA ACQUISITION
q TEST AND MEASUREMENT
q INDUSTRIAL PROCESS CONTROL
q PERSONAL DIGITAL ASSISTANTS
q BATTERY-POWERED SYSTEMS
DESCRIPTION
The ADS8344 is an 8-channel, 16-bit sampling ana-
log-to-digital converter (ADC) with a synchronous
serial interface. Typical power dissipation is 10mW at
a 100kHz throughput rate and a +5V supply. The
reference voltage (VREF) can be varied between 500mV
and V , providing a corresponding input voltage
CC
range of 0V to VREF. The device includes a shutdown
mode which reduces power dissipation to under 15µW.
The ADS8344 is guaranteed down to 2.7V operation.
Low power, high speed, and on-board multiplexer
make the ADS8344 ideal for battery operated systems
such as personal digital assistants, portable multi-
channel data loggers, and measurement equipment.
The serial interface also provides low-cost isolation
for remote data acquisition. The ADS8344 is available
in a QSOP-20 or a SSOP-20 package and is guaran-
teed over the –40°C to +85°C temperature range.
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
VREF
Eight
Channel
Multiplexer
SAR
CDAC
Comparator
Serial
Interface
and
Control
DCLK
CS
SHDN
DIN
DOUT
BUSY
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
©2000 Burr-Brown Corporation
PDS-11571A
ADPriSnte8d 3in4U.4S.A. April, 2000
®
1 page  
TYPICAL PERFORMANCE CURVES: +5V
At TA = +25°C, +VCC = +5V, VREF = +5V, fSAMPLE = 100kHz, and fCLK = 24 • fSAMPLE = 2.4MHz, unless otherwise noted.
0
–20
–40
–60
–80
–100
–120
–140
–160
0
FREQUENCY SPECTRUM
(4096 Point FFT; fIN = 1.001kHz, –0.2dB)
10 20 30
Frequency (kHz)
40
50
0
–20
–40
–60
–80
–100
–120
–140
–160
0
FREQUENCY SPECTRUM
(4096 Point FFT; fIN = 9.985kHz, –0.2dB)
10 20 30
Frequency (kHz)
40
50
SIGNAL-TO-NOISE RATIO AND SIGNAL-TO-
(NOISE+DISTORTION) vs INPUT FREQUENCY
100
SNR
90
80
SINAD
70
60
1
10
Frequency (kHz)
100
SPURIOUS FREE DYNAMIC RANGE AND TOTAL
HARMONIC DISTORTION vs INPUT FREQUENCY
100 –100
SFDR
90 –90
80
THD(1)
–80
70
NOTE: (1) First Nine Harmonics
of the Input Frequency
60
1
10
Frequency (kHz)
–70
–60
100
15.0
14.5
14.0
13.5
13.0
12.5
12.0
11.5
11.0
1
EFFECTIVE NUMBER OF BITS
vs INPUT FREQUENCY
CHANGE IN SIGNAL-TO-(NOISE+DISTORTION)
vs TEMPERATURE
0.4
fIN = 9.985kHz, –0.2dB
0.2
0.0
–0.2
–0.4
–0.6
10
Frequency (kHz)
–0.8
100
–40 –25
0
20 50 75 100
Temperature (˚C)
®
5 ADS8344
5 Page 
Since one clock cycle of the serial clock is consumed with
BUSY going high (while the MSB decision is being made),
16 additional clocks must be given to clock out all 16 bits of
data; thus, one conversion takes a minimum of 25 clock
cycles to fully read the data. Since most microprocessors
communicate in 8-bit transfers, this means that an additional
transfer must be made to capture the LSB.
There are two ways of handling this requirement. One is
shown in Figure 3, where the beginning of the next control
byte appears at the same time the LSB is being clocked out
of the ADS8344. This method allows for maximum through-
put and 24 clock cycles per conversion.
The other method is shown in Figure 5, which uses 32 clock
cycles per conversion; the last seven clock cycles simply
shift out zeros on the DOUT line. BUSY and DOUT go into
a high-impedance state when CS goes high; after the next CS
falling edge, BUSY will go LOW.
Internal Clock Mode
In internal clock mode, the ADS8344 generates its own
conversion clock internally. This relieves the microproces-
sor from having to generate the SAR conversion clock and
allows the conversion result to be read back at the processor’s
convenience, at any clock rate up to 2.4MHz. BUSY goes
HIGH at the start of conversion and then returns LOW when
the conversion is complete. During the conversion, BUSY
will remain LOW for a maximum of 8µs. Also, during the
conversion, SCLK should remain LOW to achieve the best
noise performance. The conversion result is stored in an
internal register; the data may be clocked out of this register
any time after the conversion is complete.
If CS is LOW when BUSY goes LOW following a conver-
sion, the next falling edge of the external serial clock will
write out the MSB on the DOUT line. The remaining bits
(D14-D0) will be clocked out on each successive clock cycle
following the MSB. If CS is HIGH when BUSY goes LOW
then the DOUT line will remain in tri-state until CS goes
LOW (Figure 6). CS does not need to remain LOW once a
conversion has started. Note that BUSY is not tri-stated
when CS goes HIGH in internal clock mode.
Data can be shifted in and out of the ADS8344 at clock rates
exceeding 2.4MHz, provided that the minimum acquisition
time tACQ, is kept above 1.7µs.
Digital Timing
Figure 4 and Tables VI and VII provide detailed timing for
the digital interface of the ADS8344.
SYMBOL
tACQ
tDS
tDH
tDO
tDV
tTR
tCSS
tCSH
tCH
tCL
tBD
tBDV
tBTR
DESCRIPTION
Acquisition Time
DIN Valid Prior to DCLK Rising
DIN Hold After DCLK HIGH
DCLK Falling to DOUT Valid
CS Falling to DOUT Enabled
CS Rising to DOUT Disabled
CS Falling to First DCLK Rising
CS Rising to DCLK Ignored
DCLK HIGH
DCLK LOW
DCLK Falling to BUSY Rising
CS Falling to BUSY Enabled
CS Rising to BUSY Disabled
MIN
1.5
100
10
100
0
200
200
TYP MAX UNITS
µs
ns
ns
200 ns
200 ns
200 ns
ns
ns
ns
ns
200 ns
200 ns
200 ns
TABLE VI. Timing Specifications (+VCC = +2.7V to 3.6V,
TA = –40°C to +85°C, CLOAD = 50pF).
CS
DCLK
DIN
BUSY
1
Idle
S A2 A1 A0
(START)
tACQ
8
Acquire
SGL/
DIF
PD1
PD0
1
81
Conversion
81
DOUT
FIGURE 5.
15 14 13 12 11 10 9
(MSB)
8
7654321
0
(LSB)
8
Idle
Zero Filled...
CS
DCLK
DIN
BUSY
DOUT
1
Idle
S A2 A1 A0
(START)
tACQ
8
Acquire
SGL/
DIF
PD1
PD0
Conversion
FIGURE 6.
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
15 14 13 12 11 10
(MSB)
9
8
7654321
0
(LSB)
Zero Filled...
11 ADS8344
®
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet ADS8344.PDF ] | |
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