PDF ADS7891 Data sheet ( Hoja de datos )

Número de pieza	ADS7891
Descripción	14BIT 3 MSPS LOW POWER SAR ANALOG TO DIGITAL CONVERTER
Fabricantes	Burr-Brown Corporation
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No Preview Available ! ADS7891 SLAS410 − DECEMBER 2003 14ĆBIT, 3ĆMSPS LOW POWER SAR ANALOGĆTOĆDIGITAL CONVERTER FEATURES D 3 MHz Sample Rate, 14-Bit Resolution D Zero Latency D Unipolar, Pseudo Differential Input, Range: − 0 V to 2.5 V D High Speed Parallel Interface D 78 dB SNR and 88.5 dB THD at 3 MSPS D Power Dissipation 85 mW at 3 MSPS D Nap Mode (10 mW Power Dissipation) D Power Down (10 mW) D Internal Reference D Internal Reference Buffer D 8-/14-Bit Bus Transfer D 48-Pin TQFP Package APPLICATIONS D Optical Networking (DWDM, MEMS Based Switching) D Spectrum Analyzers D High Speed Data Acquisition Systems D High Speed Close-Loop Systems D Telecommunication D Ultra-Sound Detection DESCRIPTION The ADS7891 is a 14-bit 3-MSPS A-to-D converter with 2.5-V internal reference. The device includes a capacitor based SAR A/D converter with inherent sample and hold. The device offers a 14-bit parallel interface with an additional byte mode that provides easy interface with 8-bit processors. The device has a pseudo-differential input stage. The −IN swing of ±200 mV is useful to compensate for ground voltage mismatch between the ADC and sensor and also to cancel common-mode noise. With nap mode enabled, the device operates at lower power when used at lower conversion rates. The device is available in a 48-pin TQFP package. +IN −IN REFIN + _ REFOUT SAR CDAC Comparator Output Latches and 3-State Drivers BYTE 14/8-Bit Parallel Data Output Bus CLOCK 2.5 V Internal Reference Conversion and Control Logic PWD/RST A_PWD CONVST BUSY CS RD Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright  2003, Texas Instruments Incorporated 1 page www.ti.com ADS7891 SLAS410 − DECEMBER 2003 TIMING REQUIREMENTS All specifications typical at −40°C to 85°C, +VA = +5 V, +VBD = +5 V (see Notes 1, 2, 3, and 4) PARAMETER SYMBOL MIN TYP MAX UNITS REF FIG. Conversion time Acquisition time SAMPLING AND CONVERSION START t(conv) t(acq) 255 273 ns 60 78 ns 5 5 Hold time CS low to CONVST high (with BUSY high) Delay CONVST high to acquisition start Hold time, CONVST high to CS high with BUSY low Hold time, CONVST low to CS high Delay CONVST low to BUSY high CS width for acquisition or conversion to start Delay CS low to acquisition start with CONVST high Pulse width, from CS low to CONVST low for acquisition to start Delay CS low to BUSY high with CONVST low Quiet sampling time(3) th1 10 ns 3 td1 2 4 5 ns 1 th2 10 ns 1 th3 10 ns 1 td2 40 ns 1 tw3 20 ns 2 td3 2 4 5 ns 2 tw1 20 ns 2 td4 40 ns 2 25 ns CONVERSION ABORT Setup time CONVST high to CS low with BUSY high Delay time CS low to BUSY low with CONVST high DATA READ tsu1 15 ns 4 td5 20 ns 4 Delay RD low to data valid with CS low Delay BYTE high to LSB word valid with CS and RD low Delay time RD high to data 3-state with CS low Delay time end of conversion to BUSY low Quiet sampling time RD high to CONVST low Delay CS low to data valid with RD low Delay CS high to data 3-state with RD low Quiet sampling time CS low to CONVST low BACK-TO-BACK CONVERSION td6 25 ns 5 td7 25 ns 5 td9 25 ns 5 td11 20 ns 5 t1 25 ns 5 td8 25 ns 6 td10 25 ns 6 t2 25 ns 6 Delay BUSY low to data valid Pulse width, CONVST high Pulse width, CONVST low POWER DOWN/RESET td12 tw4 70 tw5 20 10 ns ns ns 7, 8 7, 8 7 Pulse width, low for PWD/RST to reset the device tw6 45 6140 ns 12 Pulse width, low for PWD/RST to power down the device tw7 7200 ns 11 Delay time, power up after PWD/RST is high td13 25 ms 11 (1) All input signals are specified with tr = tf = 5 ns (10% to 90% of +VBD) and timed from a voltage level of (VIL + VIH)/2. (2) See timing diagram. (3) Quiet period before conversion start, no data bus activity including data bus 3-state is allowed in this period. (4) All timings are measured with 20 pF equivalent loads with 5 V +VBD and 10-pF equivalent loads with 3 V +VBD on all data bits and BUSY pin. 5 5 Page www.ti.com ADS7891 SLAS410 − DECEMBER 2003 CS CONVST th1 tw4 t(acq) BUSY D13−D0 td12 Sample N tw3 t(conv) + td11 Conversion N Data For Conversion N−1 (Data read Without Latency) t0 = 333 ns for 3 MSPS Operation Figure 8. Back-To-Back operation With CS Toggling and RD Low NAP MODE The device can be put in nap mode following the sequences shown in Figure 9. This provides substantial power saving while operating at lower sampling rates. While operating the device at throughput rates lower than 2.54 MSPS, A_PWD can be held low (see Figure 9). In this condition, the device goes into the nap state immediately after BUSY goes low and remains in that state until the next sampling starts. The minimum acquisition time is 60 nsec more than t(acq) as defined in the timing requirements section. Alternately, A_PWD can be toggled any time during operation (see Figure 10). This is useful when the system acquires data at the maximum conversion speed for some period of time (back-to-back conversion) and it does not acquire data for some time while the acquired data is being processed. During this period, the device can be put in the nap state to save power. The device remains in the nap state as long as A_PWD is low with BUSY being low and sampling has not started. The minimum acquisition time for the first sampling after the nap state is 60 nsec more than t(acq) as defined in the timing requirements section. A_PWD (Held Low) BUSY SAMPLE (Internal) NAP (Internal Active High) t(acq) + 60 ns NOTE: The SAMPLE (Internal) signal is generated as described in the Sampling and Conversion Start section. Figure 9. Device Operation While A_PWD is Held Low 11 11 Page

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