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PDF ADS7864Y Data sheet ( Hoja de datos )
| Número de pieza | ADS7864Y | |
| Descripción | 500kHz/ 12-Bit/ 6-Channel Simultaneous Sampling ANALOG-TO-DIGITAL CONVERTER | |
| Fabricantes | Burr-Brown Corporation | |
| Logotipo |  |
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ADS7864
ADS7864
SBAS141
500kHz, 12-Bit, 6-Channel
Simultaneous Sampling
ANALOG-TO-DIGITAL CONVERTER
FEATURES
q 6 SIMULTANEOUS SAMPLING CHANNELS
q FULLY DIFFERENTIAL INPUTS
q 2µs TOTAL THROUGHPUT PER CHANNEL
q GUARANTEED NO MISSING CODES
q PARALLEL INTERFACE
q 1MHz EFFECTIVE SAMPLING RATE
q LOW POWER: 50mW
q 6X FIFO
APPLICATIONS
q MOTOR CONTROL
q MULTI-AXIS POSITIONING SYSTEMS
q 3-PHASE POWER CONTROL
DESCRIPTION
The ADS7864 is a dual 12-bit, 500kHz Analog-to-
Digital (A/D) converter with 6 fully differential input
channels grouped into three pairs for high speed simul-
taneous signal acquisition. Inputs to the sample-and-
hold amplifiers are fully differential and are main-
tained differential to the input of the A/D converter.
This provides excellent common-mode rejection of
80dB at 50kHz which is important in high noise
environments.
The ADS7864 offers a parallel interface and control
inputs to minimize software overhead. The output data
for each channel is available as a 16-bit word (address
and data). The ADS7864 is offered in a TQFP-48
package and is fully specified over the –40°C to +85°C
operating range.
HOLDA
CH A0+
CH A0–
HOLDB
CH B0+
CH B0–
HOLDC
CH C1+
CH C1–
REFIN
REFOUT
CH A1+
CH A1–
CH B1+
CH B1–
CH C1+
CH C1–
S/H
Amp
S/H
Amp
S/H
Amp
MUX
S/H
Amp
S/H
Amp
S/H
Amp
MUX
SAR
CDAC
COMP
Internal
2.5V
Reference
CDAC
COMP
SAR
Interface
A2
A1
Conversion
and
Control
A0
BYTE
CLOCK
CS
RD
BUSY
RESET
FIFO
Registers
Channel/
16 Data Output
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Twx: 910-952-1111 • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
http://www.burr-brown.com/
http://www.ti.com/
Copyright © 2000, Texas Instruments Incorporated
PDS-11581A
ADS7864Printed in U.S.A. September, 2000
®
1 page  
TYPICAL PERFORMANCE CURVES
At TA = +25°C, +VA = +VD = +5V, VREF = internal +2.5V and fCLK = 8MHz, fSAMPLE = 500kHz, unless otherwise noted.
0
–20
–40
–60
–80
–100
–120
0
FREQUENCY SPECTRUM
(4096 Point FFT; fIN = 99.9kHz, –0.2dB)
62.5
125 187.5
Frequency (kHz)
250
0
–20
–40
–60
–80
–100
–120
0
FREQUENCY SPECTRUM
(4096 Point FFT; fIN = 199.9kHz, –0.2dB)
62.5
125 187.5
Frequency (kHz)
250
75
70
65
60
55
50
1k
SIGNAL-TO-NOISE RATIO AND
SIGNAL-TO-(NOISE+DISTORTION)
vs INPUT FREQUENCY
SNR
SINAD
10k 100k
Input Frequency (Hz)
1M
CHANGE IN SIGNAL-TO-NOISE RATIO
AND SIGNAL-TO-(NOISE+DISTORTION)
vs TEMPERATURE
1.0
0.6
0.2 SNR
–0.2
–0.6
SINAD
–1.0
–40
–20
0 20 40
Temperature (°C)
60
80
CHANGE IN SPURIOUS FREE DYNAMIC RANGE
AND TOTAL HARMONIC DISTORTION
vs TEMPERATURE
1.0
THD
0.5
0.0
SFDR
–0.5
–1.0
–40
–20
0
20 40 60 80
Temperature (°C)
POSITIVE GAIN MATCH vs TEMPERATURE
(Maximum Deviation for All Six Channels)
1.80
1.70
1.60
1.50
1.40
1.30
1.20
–40
–20
0 20 40
Temperature (°C)
60
80
®
5 ADS7864
5 Page 
START OF A CONVERSION
By bringing one or all of the HOLDX signals low, the input
data of the corresponding channel X is immediately placed
in the hold mode (5ns). The conversion of this channel X
follows as soon as the AD-converter is available for the
particular channel. If other channels are already in the hold
mode but not converted, then the conversion of channel X is
put in the queue until the previous conversion has been
completed. If more than one channel goes into hold mode
within one clock cycle, then channel A will be converted
first if HOLDA is one of the triggered hold signals. Next
channel B will be converted and at last channel C. If it
is important to detect a hold command during a certain
clock-cycle, then the falling edge of the hold signal has to
occur at least 10ns before the falling edge of clock. (Figure
8, t1). The hold signal can remain low without initiating a
new conversion. The hold signal has to be high for at least
15ns (Figure 8, t2) before it is brought low again and hold
has to stay low for at least 20ns (Figure 8, t3).
CLOCK
HOLDA
t6 t1
t7
t3
t5
HOLDB
HOLDC
t9
t2
RESET
t8
FIGURE 8. Start of the Conversion.
In the example of Figure 8, the signal HOLDB goes low first
and channel B0 and B1 will be converted first. The falling
edges of HOLDA and HOLDC occur within the same clock
cycle. Therefore, the channels A0 and A1 will be converted
as soon as the channels B0 and B1 are finished (plus
acquisition time). When the A-channels are finished, the
C-channels will be converted. The second HOLDA signal is
ignored, as the A-channels are not converted at this point in
time.
Once a particular hold signal goes low, further impulses of
this hold signal are ignored until the conversion is finished
or the part is reset. When the conversion is finished (BUSY
signal goes high) the sampling switches will close and
sample the selected channel. The start of the next conversion
must be delayed to allow the input capacitor of the ADS7864
to be fully charged. This delay time depends on the driving
amplifier, but should be at least 175ns (Figure 9, t4).
The ADS7864 can also convert one channel continuously, as
it is shown in Figure 9 with channel B. Therefore, HOLDA
and HOLDC are kept high all the time. To gain acquisition
TIMING SPECIFICATIONS
SYMBOL
DESCRIPTION
MIN TYP MAX UNITS
t1
HOLD (A, B, C) before
10
falling edge of clock
t2
HOLD HIGH time to be
15
recognized again
t3
HOLD LOW time
20
t4
Input capacitor charge time
175
t5
Clock period
125
t6
Clock HIGH time
40
t7
Clock LOW time
40
t8
Reset pulse width
20
t9
First hold after reset
20
t10 Conversion time
12.5 • t5
t11 Successive conversion time (16 • t5) 2
t12
Address setup before RD
10
t13
CS before end of RD
30
t14
RD HIGH time
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
BUSY
CLOCK
t11
t10 t4
HOLDB
CS
RD
A0
FIGURE 9. Timing of One Conversion Cycle.
11
ADS7864
®
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet ADS7864Y.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
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