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PDF ADS7852 Data sheet ( Hoja de datos )
| Número de pieza | ADS7852 | |
| Descripción | 12-Bit/ 8-Channel/ Parallel Output ANALOG-TO-DIGITAL CONVERTER | |
| Fabricantes | Burr-Brown Corporation | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ADS7852 (archivo pdf) en la parte inferior de esta página. Total 13 Páginas | ||
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® ADS7852
ADS7852 ¤
For most current data sheet and other product
information, visit www.burr-brown.com
12-Bit, 8-Channel, Parallel Output
ANALOG-TO-DIGITAL CONVERTER
FEATURES
q 2.5V INTERNAL REFERENCE
q 8 INPUT CHANNELS
q 500kHz SAMPLING RATE
q SINGLE 5V SUPPLY
q ±1LSB: INL, DNL
q GUARANTEED NO MISSING CODES
q 70dB SINAD
q LOW POWER: 13mW
q TQFP-32 PACKAGE
APPLICATIONS
q DATA ACQUISITION
q TEST AND MEASUREMENT
q INDUSTRIAL PROCESS CONTROL
q MEDICAL INSTRUMENTS
DESCRIPTION
The ADS7852 is an 8-channel, 12-bit analog-to-digi-
tal converter (A/D) complete with sample-and-hold,
internal 2.5V reference and a full 12-bit parallel output
interface. Typical power dissipation is 13mW at at
500kHz throughput rate. The ADS7852 features both
a nap mode and a sleep mode further reducing the
power consumption to 2mW. The input range is from
0V to twice the reference voltage. The reference volt-
age can be overdriven by an external voltage.
The ADS7852 is ideal for multi-channel applications
where low power and small size are critical. Medical
instrumentation, high-speed data acquisition and labo-
ratory equipment are just a few of the applications that
would take advantage of the special features offered
by the ADS7852. The ADS7852 is available in an
TQFP-32 package and is fully specified and guaran-
teed over the –40°C to +85°C temperature range.
A0 A1 A2
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
8-Channel
MUX
VREF
ADS7852
SAR
CDAC
Comparator
Buffer
10kΩ
Internal
+2.5V Ref
Output
Latches
and
3-State
Drivers
3-State
Parallel
Data Bus
CLK
BUSY
WR
CS
RD
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
©1998 Burr-Brown Corporation
PDS-11509C
ADPrSint7ed8in5U2.S.A. May, 2000
®
1 page  
TYPICAL PERFORMANCE CURVES
At TA = +25°C, VSS = +5V, fSAMPLE = 500kHz, fCLK = 16 • fSAMPLE, and internal reference, unless otherwise specified.
0
–20
–40
–60
–80
–100
–120
0
SPECTRAL PERFORMANCE
(4096 Point FFT, fIN = 49.561kHz, –0.5dB)
50 100 150 200 250
Frequency (kHz)
0
–20
–40
–60
–80
–100
–120
0
SPECTRAL PERFORMANCE
(4096 Point FFT, fIN = 100.7081kHz, –0.5dB)
50 100 150 200 250
Frequency (kHz)
0
–20
–40
–60
–80
–100
–120
0
SPECTRAL PERFORMANCE
(4096 Point FFT, fIN = 199.5851kHz, –0.5dB)
50 100 150 200 250
Frequency (kHz)
0
–20
–40
–60
–80
–100
–120
0
SPECTRAL PERFORMANCE
(4096 Point FFT, fIN = 247.1921kHz, –0.5dB)
50 100 150 200 250
Frequency (kHz)
CHANGE IN SPURIOUS FREE DYNAMIC RANGE AND
TOTAL HARMONIC DISTORTION vs TEMPERATURE
1.0 –1.0
fIN = 49.6kHz,–0.5dB
*First nine harmonics
of the input frequency
0.5
THD*
–0.5
0.0
–0.5
SFDR
0.0
0.5
–1.0
–50
–25
0 25 50
Temperature (°C)
1.0
75 100
CHANGE IN SIGNAL-TO-NOISE RATIO AND
SIGNAL-TO-(NOISE+DISTORTION) vs TEMPERATURE
0.4
0.3 fIN = 49.6kHz,–0.5dB
0.2 SNR
0.1
SINAD
0.0
–0.1
–0.2
–0.3
–0.4
–0.5
–50
–25
0 25 50
Temperature (°C)
75 100
®
5 ADS7852
5 Page 
CLK
WR
CS
BUSY
RD
Address
Bus
Data
Bus
HOLD
tCKH
tCKP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8
t1 t2
tCKL
t4
t3
t5
Conversion n
tCONV
Address n + 1
Hi-Z
t4
tACQ
t6
t7
t8
t9
Data
Valid
Conversion n + 1
Address n + 2
t10
Hi-Z
Data
Valid
Hi-Z
SYMBOL
tCONV
tACQ
tCKP
tCKL
tCKH
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
DESCRIPTION
Conversion Time
Acquisition Time
Clock Period
Clock LOW
Clock HIGH
WR LOW Prior to Rising Edge of CLK
WR LOW After Rising Edge of CLK
CS LOW After Rising Edge of CLK
CS and RD HIGH
BUSY Delay After CS LOW
RD LOW
Address Hold Time
Address Setup Time
Bus Access Time
Bus Relinquish Time
CS to RD Setup Time
RD to CS Hold Time
CLK LOW to BUSY HIGH
BUSY to RD Delay
RD HIGH to CLK LOW
MIN TYP MAX UNITS
1.75 µs
0.25 µs
125 5000 ns
40 ns
40 ns
35 ns
20 ns
20 ns
25 ns
20 ns
25 ns
5 ns
5 ns
30 ns
5 ns
0 ns
0 ns
10 ns
0 ns
50 ns
FIGURE 2. ADS7852 Write/Read Timing.
READING DATA
Data from the ADS7852 will appear at pins 15 through 26.
The MSB will output on pin 15 while the LSB will output
on pin 26. The outputs are coded in Straight Binary (with
0V = 000H and 5V = FFFH). Following a conversion, the
BUSY pin will go HIGH. After BUSY has been HIGH for
at least t14 seconds, the CS and RD pins may be brought
LOW to enable the 12-bit output bus. CS and RD must be
held LOW for at least 25ns following BUSY HIGH. Data
will be valid 30ns after the falling edge of both CS and RD.
The output data will remain valid for 20ns following the
rising edge of both CS and RD. See Figure 2 for the read
cycle timing diagram.
DESCRIPTION
Least Significant
Bit (LSB)
Full Scale
Midscale
Midscale –1LSB
Zero Full Scale
ANALOG INPUT
1.2207mV
4.99878V
2.5V
2.49878V
0V
DIGITAL OUTPUT
STRAIGHT BINARY
BINARY CODE
HEX CODE
1111 1111 1111
1000 0000 0000
0111 1111 1111
0000 0000 0000
FFF
800
7FF
000
Table I. Ideal Input Voltages and Output Codes.
®
11 ADS7852
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet ADS7852.PDF ] | |
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