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PDF ADS7844E Data sheet ( Hoja de datos )
| Número de pieza | ADS7844E | |
| Descripción | 12-Bit/ 8-Channel Serial Output Sampling ANALOG-TO-DIGITAL CONVERTER | |
| Fabricantes | Burr-Brown Corporation | |
| Logotipo |  |
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® ADS7844
ADS7844
ADS7844
12-Bit, 8-Channel Serial Output Sampling
ANALOG-TO-DIGITAL CONVERTER
FEATURES
q SINGLE SUPPLY: 2.7V to 5V
q 8-CHANNEL SINGLE-ENDED OR
4-CHANNEL DIFFERENTIAL INPUT
q UP TO 200kHz CONVERSION RATE
q ±1 LSB MAX INL AND DNL
q GUARANTEED NO MISSING CODES
q 72dB SINAD
q SERIAL INTERFACE
q 20-LEAD QSOP AND
20-LEAD SSOP PACKAGES
q ALTERNATE SOURCE FOR MAX147
APPLICATIONS
q DATA ACQUISITION
q TEST AND MEASUREMENT
q INDUSTRIAL PROCESS CONTROL
q PERSONAL DIGITAL ASSISTANTS
q BATTERY-POWERED SYSTEMS
DESCRIPTION
The ADS7844 is an 8-channel, 12-bit sampling ana-
log-to-digital converter (ADC) with a synchronous
serial interface. Typical power dissipation is 3mW at
a 200kHz throughput rate and a +5V supply. The
reference voltage (V ) can be varied between 100mV
REF
and VCC, providing a corresponding input voltage
range of 0V to VREF. The device includes a shutdown
mode which reduces power dissipation to under 1µW.
The ADS7844 is guaranteed down to 2.7V operation.
Low power, high speed, and on-board multiplexer
make the ADS7844 ideal for battery operated systems
such as personal digital assistants, portable multi-
channel data loggers, and measurement equipment.
The serial interface also provides low-cost isolation
for remote data acquisition. The ADS7844 is available
in a 20-lead QSOP package and the MAX147 equiva-
lent 20-lead SSOP package and is guaranteed over the
–40°C to +85°C temperature range.
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
VREF
Eight
Channel
Multiplexer
SAR
CDAC
Comparator
Serial
Interface
and
Control
DCLK
CS
SHDN
DIN
DOUT
BUSY
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
©1998 Burr-Brown Corporation
PDS-1463D
Printed in U.S.A. July, 1999
1 page  
TYPICAL PERFORMANCE CURVES:+5V
At TA = +25°C, +VCC = +5V, VREF = +5V, fSAMPLE = 200kHz, and fCLK = 16 • fSAMPLE = 3.2MHz, unless otherwise noted.
0
–20
–40
–60
–80
–100
–120
0
FREQUENCY SPECTRUM
(4096 Point FFT; fIN = 1,123Hz, –0.2dB)
25 50 75
Frequency (kHz)
100
0
–20
–40
–60
–80
–100
–120
0
FREQUENCY SPECTRUM
(4096 Point FFT; fIN = 10.3kHz, –0.2dB)
25 50 75
Frequency (kHz)
100
SIGNAL-TO-NOISE RATIO AND SIGNAL-TO-
(NOISE+DISTORTION) vs INPUT FREQUENCY
74
SNR
73
72
SINAD
71
70
69
68
1
10
Input Frequency (kHz)
100
SPURIOUS FREE DYNAMIC RANGE AND TOTAL
HARMONIC DISTORTION vs INPUT FREQUENCY
85 –85
SFDR
80 –80
THD
75 –75
70 –70
65
1
10
Input Frequency (kHz)
–65
100
12.0
11.8
11.6
11.4
11.2
11.0
1
EFFECTIVE NUMBER OF BITS
vs INPUT FREQUENCY
10
Input Frequency (kHz)
100
CHANGE IN SIGNAL-TO-(NOISE+DISTORTION)
vs TEMPERATURE
0.6
0.4
0.2
0.0
–0.2
–0.4
fIN = 10kHz, –0.2dB
–0.6
–40
–20
0
20 40
Temperature (°C)
60
80 100
®
5 ADS7844
5 Page 
Bit 7
(MSB)
S
Bit 6
A2
Bit 5
A1
Bit 4
A0
Bit 3 Bit 2
— SGL/DIF
Bit 1
PD1
Bit 0
(LSB)
PD0
TABLE III. Order of the Control Bits in the Control Byte.
BIT NAME DESCRIPTION
7 S Start Bit. Control byte starts with first HIGH bit on
DIN. A new control byte starts with every 15th clock
cycle.
6-4
A2 - A0
Channel Select Bits. Along with the SGL/DIF bit,
these bits control the setting of the multiplexer input
as detailed in Tables I and II.
3 — Not Used.
2 SGL/DIF Single-Ended/Differential Select Bit. Along with bits
A2 - A0, this bit controls the setting of the multiplexer
input as detailed in Tables I and II.
1 - 0 PD1 - PD0 Power-Down Mode Select Bits. See Table V for
details.
TABLE IV. Descriptions of the Control Bits within the
Control Byte.
The SGL/DIF bit controls the multiplexer input mode: either
single-ended (HIGH) or differential (LOW). In single-ended
mode, the selected input channel is referenced to the COM
pin. In differential mode, the two selected inputs provide a
differential input. See Tables I and II and Figure 2 for more
information. The last two bits (PD1 - PD0) select the power-
down mode as shown in Table V. If both inputs are HIGH,
the device is always powered up. If both inputs are LOW, the
device enters a power-down mode between conversions.
When a new conversion is initiated, the device will resume
normal operation instantly—no delay is needed to allow the
device to power up and the very first conversion will be
valid.
16-Clocks per Conversion
The control bits for conversion n+1 can be overlapped with
conversion ‘n’ to allow for a conversion every 16 clock
cycles, as shown in Figure 4. This figure also shows possible
serial communication occurring with other serial peripherals
between each byte transfer between the processor and the
converter. This is possible provided that each conversion
completes within 1.6ms of starting. Otherwise, the signal
that has been captured on the input sample/hold may droop
enough to affect the conversion result. In addition, the
ADS7844 is fully powered while other serial communica-
tions are taking place.
CS
DCLK
1
tACQ
8
1
81
8
DIN
BUSY
S A2
(START)
A1 A0
Idle
SGL/
DIF
PD1
PD0
Acquire
Conversion
Idle
DOUT
11 10 9 8 7 6 5
(MSB)
4
3210
(LSB)
Zero Filled...
FIGURE 3. Conversion Timing, 24-Clocks per Conversion, 8-Bit Bus Interface. No DCLK delay required with dedicated
serial port.
CS
DCLK
DIN
BUSY
18
S
CONTROL BITS
1
81
8
S
CONTROL BITS
1
DOUT
11 10 9 8 7 6 5
43 2 1 0
11 10 9
FIGURE 4. Conversion Timing, 16-Clocks per Conversion, 8-bit Bus Interface. No DCLK delay required with dedicated
serial port.
®
11 ADS7844
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet ADS7844E.PDF ] | |
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