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PDF ADS7835EB Data sheet ( Hoja de datos )
| Número de pieza | ADS7835EB | |
| Descripción | 12-Bit/ High-Speed/ Low Power Sampling ANALOG-TO-DIGITAL CONVERTER | |
| Fabricantes | Burr-Brown Corporation | |
| Logotipo |  |
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® ADS7835
For most current data sheet and other product
information, visit www.burr-brown.com
12-Bit, High-Speed, Low Power Sampling
ANALOG-TO-DIGITAL CONVERTER
FEATURES
q 500kHz THROUGHPUT RATE
q 2.5V INTERNAL REFERENCE
q LOW POWER: 17.5mW
q SINGLE SUPPLY +5V OPERATION
q SERIAL INTERFACE
q GUARANTEED NO MISSING CODES
q MSOP-8
q ±VREF INPUT RANGE
APPLICATIONS
q BATTERY-OPERATED SYSTEMS
q DIGITAL SIGNAL PROCESSING
q HIGH-SPEED DATA ACQUISITION
q WIRELESS COMMUNICATION SYSTEMS
DESCRIPTION
The ADS7835 is a 12-bit, sampling analog-to-digi-
tal converter (A/D) complete with sample-and-hold
(S/H), internal 2.5V reference, and synchronous
serial interface. Typical power dissipation is 17.5mW
at a 500kHz throughput rate. The device can be
placed into a power-down mode which reduces dis-
sipation to just 2.5mW. The input range is –VREF to
+VREF, and the internal reference can be overdriven
by an external voltage.
Low power, small size, and high speed make the
ADS7835 ideal for battery-operated systems such
as wireless communication devices, portable multi-
channel data loggers, and spectrum analyzers. The
serial interface also provides low cost isolation for
remote data acquisition. The ADS7835 is avail-
able in an MSOP-8 package and is guaranteed over
the –40°C to +85°C temperature range.
SAR
CLK
CONV
±2.5V
Input
2kΩ
2kΩ
S/H Amp
CDAC
Comparator
Serial
Interface
DATA
Buffer
Internal
+2.5V Ref
VREF
10kΩ ±30%
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
©1998 Burr-Brown Corporation
PDS-11478B
ADPSrin7ted8i3n U5.S.A.May, 2000
®
1 page  
TYPICAL PERFORMANCE CURVES (Cont.)
At TA = +25°C, +VCC = +5V, fSAMPLE = 500kHz, fCLK = 16 • fSAMPLE, and internal +2.5V reference, unless otherwise specified.
4.0
3.0
2.0
1.0
0.0
–1.0
–2.0
–3.0
–4.0
–5.0
2.2
CHANGE END-POINT ERRORS
vs EXTERNAL REFERENCE VOLTAGE
Negative Full-Scale Error
Positive Full-Scale Error
and Bipolar Offset Error
2.4 2.6 2.8
External Reference Voltage (V)
3.0
0.90
0.85
0.80
0.75
0/70
0.65
0.60
0.55
0.50
2
PEAK-TO-PEAK NOISE
vs EXTERNAL REFERENCE VOLTAGE
2.1 2.2 2.3 2.4
External Reference Voltage (V)
2.5
30
25
20
15
10
5
0
1
POWER SUPPLY REJECTION RATIO
vs POWER SUPPLY RIPPLE FREQUENCY
10 100 1k 10k 100k
Power Supply Ripple Frequency (Hz)
1M
0
–20
–40
–60
–80
–100
–120
0
FREQUENCY SPECTRUM
(4096 Point FFT; fIN = 977Hz, –0.2dB)
50 100 150 200 250
Frequency (kHz)
0
–20
–40
–60
–80
–100
–120
0
FREQUENCY SPECTRUM
(4096 Point FFT; fIN = 9.77kHz, –0.2dB)
50 100 150 200 250
Frequency (kHz)
0
–20
–40
–60
–80
–100
–120
0
FREQUENCY SPECTRUM
(4096 Point FFT; fIN = 99.7kHz, –0.2dB)
50 100 150 200 250
Frequency (kHz)
®
5 ADS7835
5 Page 
500kHz conversion rate.
fSAMPLE
500kHz
250kHz
100kHz
POWER WITH
CLK = 16 • fSAMPLE
17.5mW
16.5mW
15.5mW
POWER WITH
CLK = 8MHz
17.5mW
13.5mW
10.5mW
TABLE II. Power Consumption versus CLK Input.
Table II offers a look at the two different modes of operation
and the difference in power consumption.
LSB-FIRST DATA TIMING
Figure 5 shows a method to transmit the digital result in a
LSB format. This mode is entered when CONV is pulled
HIGH during the conversion (before the end of the 12th
clock) and then pulled LOW during the 13th clock (when
D0, the LSB, is being transmitted). The next 11 clocks then
repeat the serial data, but in an LSB-first format. The
converter enters the power-down mode during the 13th
clock and resumes normal operation when CONV goes
HIGH.
SHORT-CYCLE TIMING
The conversion currently in progress can be “short-cycled”
with the technique shown in Figure 6. This term means that
the conversion will terminate immediately, before all 12 bits
have been decided. This can be a very useful feature when
a resolution of 12 bits is not needed. An example would be
when the converter is being used to monitor an input voltage
until some condition is met. At that time, the full resolution
of the converter would then be used. Short-cycling the
conversion can result in a faster conversion rate or lower
power dissipation.
There are several very important items shown in Figure 6.
The conversion currently in progress is terminated when
CONV is taken HIGH during the conversion and then taken
LOW prior to tCKCH before the start of the 13th clock cycle.
Note that if CONV goes LOW during the 13th clock cycle,
the LSB-first mode will be entered (Figure 5). Additionally,
when CONV goes LOW, the DATA output immediately
transitions to high impedance. If the output bit that is present
during that clock period is needed, CONV must not go LOW
until the bit has been properly latched into the receiving
CONV
CLK
DATA
(1)
tCVH
12 34567
D11
(MSB)
D10
D9
D8 D7 D6
tCVDD
tCVL
SAMPLE/HOLD
MODE
SAMPLE
HOLD
INTERNAL
CONVERSION
STATE
IDLE
POWER MODE
CONVERSION IN PROGRESS
FULL POWER
tCVPD
IDLE
LOW POWER
NOTE: (1) The conversion currently in progress can be stopped by pulling CONV LOW during the conversion. This must occur at
least tCKCS prior to the start of the 13th clock cycle. The DATA output pin will tri-state and the device will enter the power-down
mode when CONV is pulled LOW.
FIGURE 6. Short-Cycle Timing.
®
11 ADS7835
11 Page | ||
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| PDF Descargar | [ Datasheet ADS7835EB.PDF ] | |
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