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PDF ADS7834P Data sheet ( Hoja de datos )
| Número de pieza | ADS7834P | |
| Descripción | 12-Bit High Speed Low Power Sampling ANALOG-TO-DIGITAL CONVERTER | |
| Fabricantes | Burr-Brown Corporation | |
| Logotipo |  |
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®
ADS7834
ADS7834
For most current data sheet and other product
information, visit www.burr-brown.com
12-Bit High Speed Low Power Sampling
ANALOG-TO-DIGITAL CONVERTER
FEATURES
q 500kHz THROUGHPUT RATE
q 2.5V INTERNAL REFERENCE
q LOW POWER: 11mW
q SINGLE SUPPLY +5V OPERATION
q DIFFERENTIAL INPUT
q SERIAL INTERFACE
q GUARANTEED NO MISSING CODES
q MINI-DIP-8 AND MSOP-8
q 0V TO VREF INPUT RANGE
APPLICATIONS
q BATTERY OPERATED SYSTEMS
q DIGITAL SIGNAL PROCESSING
q HIGH SPEED DATA ACQUISITION
q WIRELESS COMMUNICATION SYSTEMS
DESCRIPTION
The ADS7834 is a 12-bit sampling analog-to-digital
converter (A/D) complete with sample/hold, internal
2.5V reference, and synchronous serial interface. Typi-
cal power dissipation is 11mW at a 500kHz through-
put rate. The device can be placed into a power-down
mode which reduces dissipation to just 2.5mW. The
input range is zero to the reference voltage, and the
internal reference can be overdriven by an external
voltage.
Low power, small size, and high-speed make the
ADS7834 ideal for battery operated systems such as
wireless communication devices, portable multi-chan-
nel data loggers, and spectrum analyzers. The serial
interface also provides low-cost isolation for remote
data acquisition. The ADS7834 is available in a plastic
mini-DIP-8 or an MSOP-8 package and is guaranteed
over the –40°C to +85°C temperature range.
SAR
CLK
CONV
+In
–In
S/H Amp
CDAC
Comparator
Serial
Interface
DATA
VREF
Buffer
Internal
+2.5V Ref
10kΩ ±30%
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
©1998 Burr-Brown Corporation
PDS-11457B
ADPrSint7ed8in3U4.S.A. May, 2000
®
1 page  
TYPICAL PERFORMANCE CURVES (Cont.)
At TA = +25°C, VCC = +5V, fSAMPLE = 500kHz, fCLK = 16 • fSAMPLE, and internal +2.5V reference, unless otherwise specified.
0.300
0.200
0.100
0.000
–0.100
–0.200
–0.300
–0.400
–0.500
–0.600
2.0
FULL-SCALE ERROR
vs EXTERNAL REFERENCE VOLTAGE
2.1 2.2 2.3 2.4
External Reference Voltage (V)
2.5
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
–0.8
2.0
OFFSET VOLTAGE vs EXTERNAL
REFERENCE VOLTAGE
2.2 2.4
External Reference Voltage (V)
2.55
0.90
0.85
0.80
0.75
0/70
0.65
0.60
0.55
0.50
2
PEAK-TO-PEAK NOISE
vs EXTERNAL REFERENCE VOLTAGE
2.1 2.2 2.3 2.4
External Reference Voltage (V)
2.5
30
25
20
15
10
5
0
1
POWER SUPPLY REJECTION
vs POWER SUPPLY RIPPLE FREQUENCY
10 100 1k 10k 100k
Power Supply Ripple Frequency (Hz)
1M
0
–20
–40
–60
–80
–100
–120
0
FREQUENCY SPECTRUM
(4096 Point FFT; fIN = 977Hz, –0.2dB)
50 100 150 200 250
Frequency (kHz)
0
–20
–40
–60
–80
–100
–120
0
FREQUENCY SPECTRUM
(4096 Point FFT; fIN = 9.77kHz, –0.2dB)
50 100 150 200 250
Frequency (kHz)
®
5 ADS7834
5 Page 
Table II offers a look at the two different modes of operation
and the difference in power consumption.
fSAMPLE
500kHz
250kHz
100kHz
POWER WITH
CLK = 16 • fSAMPLE
11mW
10mW
9mW
POWER WITH
CLK = 8MHz
11mW
7mW
4mW
TABLE II. Power Consumption versus CLK Input.
LSB FIRST DATA TIMING
Figure 5 shows a method to transmit the digital result in a
least-significant bit (LSB) format. This mode is entered
when CONV is pulled HIGH during the conversion (before
the end of the 12th clock) and then pulled LOW during the
13th clock (when D0, the LSB, is being transmitted). The
next 11 clocks then repeat the serial data, but in an LSB first
format. The converter enters the power-down mode during
the 13th clock and resumes normal operation when CONV
goes HIGH.
SHORT-CYCLE TIMING
The conversion currently in progress can be “short-cycled”
with the technique shown in Figure 6. This term means that
the conversion will terminate immediately, before all 12 bits
have been decided. This can be a very useful feature when
a resolution of 12 bits is not needed. An example would be
when the converter is being used to monitor an input voltage
until some condition is met. At that time, the full resolution
of the converter would then be used. Short-cycling the
conversion can result in a faster conversion rate or lower
power dissipation.
There are several very important items shown in Figure 6.
The conversion currently in progress is terminated when
CONV is taken HIGH during the conversion and then taken
LOW prior to tCKCH before the start of the 13th clock cycle.
Note that if CONV goes LOW during the 13th clock cycle,
then the LSB-first mode will be entered (Figure 5). Also,
when CONV goes LOW, the DATA output immediately
transitions to high impedance. If the output bit that is present
during that clock period is needed, CONV must not go LOW
until the bit has been properly latched into the receiving
logic.
DATA FORMAT
The ADS7834 output data is in straight binary format as
shown in Figure 7. This figure shows the ideal output code
for the given input voltage and does not include the effects
of offset, gain, or noise.
CONV
CLK
DATA
(1)
tCVH
12 34567
D11
(MSB)
D10
D9
D8 D7 D6
tCVDD
tCVL
SAMPLE/HOLD
MODE
SAMPLE
HOLD
INTERNAL
CONVERSION
STATE
IDLE
POWER MODE
CONVERSION IN PROGRESS
FULL POWER
tCVPD
IDLE
LOW POWER
NOTE: (1) The conversion currently in progress can be stopped by pulling CONV LOW during the conversion. This must occur at
least tCKCS prior to the start of the 13th clock cycle. The DATA output pin will tri-state and the device will enter the power-down
mode when CONV is pulled LOW.
FIGURE 6. Short-cycle Timing.
11
ADS7834
®
11 Page | ||
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| PDF Descargar | [ Datasheet ADS7834P.PDF ] | |
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