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PDF ADS7832 Data sheet ( Hoja de datos )
| Número de pieza | ADS7832 | |
| Descripción | Autocalibrating/ 4-Channel/ 12-Bit ANALOG-TO-DIGITAL CONVERTER | |
| Fabricantes | Burr-Brown Corporation | |
| Logotipo |  |
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®
ADS7832
ADS7832
ADS7832
Autocalibrating, 4-Channel, 12-Bit
ANALOG-TO-DIGITAL CONVERTER
FEATURES
q PIN COMPATIBLE TO ADC7802 AND
ADS7803
q SINGLE SUPPLY: +5V OR +3.3V
q LOW POWER: 14mW plus Power Down
q SIGNAL-TO-(NOISE + DISTORTION)
RATIO OVER TEMPERATURE:
69dB min with fIN = 1kHz
66dB min with fIN = 50kHz
q FAST CONVERSION TIME: 8.5µs
Including Acquisition (117kHz Sampling
Rate)
q FOUR-CHANNEL INPUT MULTIPLEXER
q AUTOCAL: No offset or Gain Adjust
Required
DESCRIPTION
The ADS7832 is a monolithic CMOS 12-bit analog-
to-digital converter with internal sample/hold and four-
channel multiplexer. It is designed and tested for full
dynamic performance with input signals to 50kHz.
The 5V single-supply requirements and standard CS,
RD, and WR control signals make the part easy to use
in microprocessor applications. Conversion results are
available in two bytes through an 8-bit three-state
output bus.
The ADS7832 is available in a 28-pin plastic DIP and
28-lead PLCC, fully specified for operation over the
industrial –40°C to +85°C temperature range.
A0 Address
Calibration
Latch and
Microcontroller
A1 Decoder
and Memory
Clock
Control
Logic
CS
RD
WR
SFR
AIN0
AIN1
AIN2
AIN3
Analog
Multiplexer
Capacitor Array
Sampling ADC
VREF+ VREF–
Three-State
Input/Output
BUSY
8-Bit
Data Bus
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
©1996 Burr-Brown Corporation
PDS-1332B
Printed in U.S.A. April, 1998
1 page  
SPECIFICATIONS (CONT)
ADS7832 Electrical Specifications with 5V Supply
VA = VD = 5V ±10%; VREF+ = 5V; VREF– = AGND = DGND = 0V; CLK = 1MHz external 50% ±2% Duty Cycle, TA = –40°C to +85°C, after calibration at any temperature, unless
otherwise specified.
PARAMETER
CONDITIONS
ADS7832BP/ADS7832BN
MIN
TYP
MAX
UNITS
AC ACCURACY
Signal-to-(Noise + Distortion) Ratio
Total Harmonic Distortion
Signal-to-Noise Ratio
Spurious Free Dynamic Range
DIGITAL INPUTS
Voltage Levels: VIL
VIH
VIL
VIH
Current Levels: IIL
IIL
IIH
IIH
IIH
IIH
DIGITAL OUTPUTS
Data Format
Data Coding
VOL
VOH
Leakage Current
Output Capacitance
CALIBRATION TIMING
Calibration Cycle
Calibration Cycle
DIGITAL TIMING
Bus Access Time
Bus Relinquish Time
POWER SUPPLIES
Supply Voltage for Specified Performance: VA
VD
Supply Current: IA
ID
Power Dissipation
TEMPERATURE RANGE
Specification
Storage
fIN = 1kHz
fIN = 50kHz
fIN = 50kHz
fIN = 50kHz
fIN = 1kHz
fIN = 50kHz
CLK
CLK
All Others
All Others
CAL (Internal Pull-Up)
All Other Inputs
SFR (Internal Pull-Down)
CLK
All Other Inputs
Power Down Mode (SFR D3 HIGH)
Parallel 12 Bits in Two Bytes
Straight Binary
ISINK = 1.6mA
ISOURCE = 200µA
High-Z State
High-Z State
Power On or Power Failure
During Normal Operation
Tested at 5.5V
Tested at 5.5V
Tested at 5.5V
Tested at 5.5V
Power Up Mode or During Conversion
Power Down Mode, No Clock Running
69
66
–0.3
3.5
–0.3
2.4
4
–40
–65
71 dB(1)
69 dB
–75 dB
70 dB
85 dB
82 dB
0.8 V
VD +0.3V
0.8
V
V
VD +0.3V
10
V
µA
±10 µA
90 µA
1.5 mA
±10 µA
±100
nA
0.4 V
V
±1 µA
4 pF
37393
4625
Clock Cycles
Clock Cycles
83 ns
83 ns
5 5.5
5 5.5
2.5 5.5
300 500
14
50
V
V
mA
µA
mW
µW
85 °C
150 °C
TThese specifications need to be added based on performance of final silicon.
NOTES: (1) All specifications in dB are referred to a full-scale input range. (2) Over this range, total error will typically not exceed ±1LSB. (3) In this mode, the ADS7832
acquires the input signal for five clock cycles after a start command, before the input is held and conversion begins. (4) LSB means Least Significant Bit. For a 0V to
5V input range, one LSB is 1.22mV. For a 0V to 2.5V input range, one LSB is 610µV.
®
5 ADS7832
5 Page 
and any data written to the SFR has been lost. Thus, the
ADS7832 will again be in the Transparent Mode. Writing a
LOW to D5 in the SFR resets the Power Fail flag. The Cal
Error flag in the SFR is set when an overflow occurs during
calibration, which may happen in very noisy systems. It is
reset by starting a calibration, and remains low after a
calibration without an overflow is completed.
Table III shows how instructions can be transferred to the
Special Function Register by driving HBE HIGH (with SFR
HIGH) and initiating a write cycle (driving WR and CS
LOW with RD HIGH.) Note that writing to the SFR also
initiates a new conversion.
POWER DOWN MODE
Writing a HIGH to D3 in the SFR puts the ADS7832 in the
Power Down Mode. Power consumption is reduced to 50µW
and D3 remains HIGH. The internal clock and analog
circuitry are turned off, although the output registers and
SFR can still be accessed normally. To exit Power Down
Mode, either write a LOW to D3 in the SFR, or initiate a
calibration by sending a LOW to the CAL pin or writing
a HIGH to D1. Note that if the power supply falls below 3V
and then recovers, a calibration is automatically initiated,
and the SFR will be reset. D3 will be HIGH, and the
ADS7832 will be in the Power Down Mode.
During Power Down Mode, a pulse on CS and WR will
initiate a single conversion, then the ADS7832 will revert to
power down. Also, writing to D1 and D3 in the SFR will
initiate a calibration, do a single conversion and revert to the
Power Down Mode, in 4,625 clock cycles. Accurate conver-
sion results will be available in the output registers.
The activation delay from power down to normal operation
is included in the sampling time. No extra time is required,
either when coming out of the Power Down Mode or when
making a single conversion in the Power Down Mode.
SAMPLE/HOLD CONTROL MODE
With D2 in the SFR HIGH, a rising edge input on pin 26 will
switch the ADS7832 from sample-mode to hold-mode with
a 5ns aperture delay. This also initiates a conversion, which
will start within 1.5 CLK cycles.
This mode allows full control over the sample-to-hold tim-
ing, which is especially useful where external events trigger
sampling timing.
CS
WR
HBE
SFR
t1
t5
D0 - D7
t2
Valid Data
t16
FIGURE 5. Writing to the SFR.
t3
t6
VIH
VIL
t17
CS
RD
HBE
SFR
t8
t11
t11
t13
D0 - D7
t10
t12
t12
VIH
SFR Data
t14
FIGURE 6. Reading the FSR.
In the Sample/Hold Control Mode, pin 26 must be held
LOW a minimum of 2.5µs between conversions to allow
accurate acquisition of input signals. Also, offset error will
increase in this mode, since auto-zeroing of the comparator
is not synchronized to the sampling. Minimum offset is
achieved by synchronizing the sampling signal to CLK,
whether internal or external. Ideally, the sampling signal
rising edge should be delayed 20ns from the falling edge of
CLK. This will keep offset error to about 1LSB.
In the Sample/Hold Control Mode, a LOW pulse on WR
(with CS LOW) will not initiate a conversion, but the rising
edge will latch the multiplexer channel according to the
inputs on A0 and A1. When changing channels, this must be
done at least 2.5µs before pin 26 goes HIGH (to start a
conversion.)
OPERATION
CS/WR SFR/HBE
D0
D1
D2
D3
D5 D4/D6/D7
Enables Transparent Mode for Data Latches
Enables Latched Output Mode for Data Latches
Initiates Calibration Cycle
Activates Sample/Hold Control Mode
Activates Power Down Mode(2)
Resets Power Fail Flag
LOW
LOW
LOW
LOW
LOW
LOW
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
LOW
HIGH(1)
X
X
X
X
X
X
HIGH
X
X
X
X
X
X
HIGH(1)
X
X
X
X
X
X
HIGH(1)
X
X
X
X
X
X
LOW
LOW
LOW
LOW
LOW
LOW
LOW
NOTES: (1) Writing a LOW here reactivates the standard mode of operation. (2) In Power Down Mode, a pulse on CS and WR will initiate a single conversion,
then the ADS7832 will revert to power down. (3) X means it can be either HIGH or LOW without affecting this action. Writing HIGH to D4 or D6, or writing with
SFR HIGH and HBE LOW, may result in unpredictable behavior. These modes are reserved for factory use at this time.
TABLE III. Writing to the Special Function Register.
®
11 ADS7832
11 Page | ||
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| PDF Descargar | [ Datasheet ADS7832.PDF ] | |
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