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PDF ADS7816C Data sheet ( Hoja de datos )
| Número de pieza | ADS7816C | |
| Descripción | 12-Bit High Speed Micro Power Sampling ANALOG-TO-DIGITAL CONVERTER | |
| Fabricantes | Burr-Brown Corporation | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ADS7816C (archivo pdf) en la parte inferior de esta página. Total 13 Páginas | ||
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®
ADS7816
OAPDSA7681568
ADS7816
12-Bit High Speed Micro Power Sampling
ANALOG-TO-DIGITAL CONVERTER
FEATURES
q 200kHz SAMPLING RATE
q MICRO POWER:
1.9mW at 200kHz
150µW at 12.5kHz
q POWER DOWN: 3µA Max
q 8-PIN MINI-DIP, SOIC, AND MSOP
q DIFFERENTIAL INPUT
q SERIAL INTERFACE
APPLICATIONS
q BATTERY OPERATED SYSTEMS
q REMOTE DATA ACQUISITION
q ISOLATED DATA ACQUISITION
DESCRIPTION
The ADS7816 is a 12-bit, 200kHz sampling analog-
to-digital converter. It features low power operation
with automatic power down, a synchronous serial
interface, and a differential input. The reference volt-
age can be varied from 100mV to 5V, with a corre-
sponding resolution from 24µV to 1.22mV.
Low power, automatic power down, and small size
make the ADS7816 ideal for battery operated systems
or for systems where a large number of signals must be
acquired simultaneously. It is also ideal for remote
and/or isolated data acquisition. The ADS7816 is
available in an 8-pin plastic mini-DIP, an 8-lead SOIC,
or an 8-lead MSOP package.
VREF
+In
–In
S/H Amp
SAR
CDAC
Comparator
Control
Serial
Interface
DOUT
DCLOCK
CS/SHDN
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
©1996 Burr-Brown Corporation
PDS-1355B
Printed in U.S.A., March, 1997
1 page  
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, VCC = +5V, VREF = +5V, fSAMPLE = 200kHz, and fCLK = 16 • fSAMPLE, unless otherwise specified.
POWER SUPPLY REJECTION vs RIPPLE FREQUENCY
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
1
10 100 1000
Ripple Frequency (kHz)
10000
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
FREQUENCY SPECTRUM
(2048 Point FFT; fIN = 9.9kHz, –0.5dB)
25 50
Frequency (kHz)
75
100
100
90
80
70
60
50
40
30
20
10
0
1
SPURIOUS FREE DYNAMIC RANGE and
SIGNAL-TO-NOISE RATIO vs FREQUENCY
Spurious Free Dynamic Range
Signal-to-Noise Ratio
10
Frequency (kHz)
100
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
1
TOTAL HARMONIC DISTORTION vs FREQUENCY
10
Frequency (kHz)
100
SIGNAL-TO-(NOISE + DISTORTION) vs FREQUENCY
100
90
80
70
60
50
40
30
20
10
0
1 10 100
Frequency (kHz)
SIGNAL-TO-(NOISE + DISTORTION) vs INPUT LEVEL
80
70
60
50
40
30
20
10
0
–40 –35 –30 –25 –20 –15 –10
Input Level (dB)
–5
0
®
5 ADS7816
5 Page 
converter not only uses power on each DCLOCK transition
(as is typical for digital CMOS components) but also uses
some current for the analog circuitry, such as the compara-
tor. The analog section dissipates power continuously, until
the power down mode is entered.
Figure 3 shows the current consumption of the ADS7816
versus sample rate. For this graph, the converter is clocked
at 3.2MHz regardless of the sample rate—CS is HIGH for
the remaining sample period. Figure 4 also shows current
consumption versus sample rate. However, in this case, the
DCLOCK period is 1/16th of the sample period—CS is
HIGH for one DCLOCK cycle out of every 16.
There is an important distinction between the power down
mode that is entered after a conversion is complete and the
full power down mode which is enabled when CS is HIGH.
While both power down the analog section, the digital section
is powered down only when CS is HIGH. Thus, if CS is left
LOW at the end of a conversion and the converter is continu-
ally clocked, the power consumption will not be as low as
when CS is HIGH. See Figure 5 for more information.
By lowering the reference voltage, the ADS7816 requires
less current to completely charge its internal capacitors on
both the analog input and the reference input. This reduction
in power dissipation should be weighed carefully against the
resulting increase in noise, offset, and gain error as outlined
in the Reference section. The power dissipation of the
ADS7816 is reduced roughly 10% when the reference volt-
age and input range are changed from 5V to 100mV.
SHORT CYCLING
Another way of saving power is to utilize the CS signal to
short cycle the conversion. Because the ADS7816 places the
latest data bit on the DOUT line as it is generated, the
converter can easily be short cycled. This term means that
the conversion can be terminated at any time. For example,
if only 8-bits of the conversion result are needed, then the
conversion can be terminated (by pulling CS HIGH) after
the 8th bit has been clocked out.
This technique can be used to lower the power dissipation
(or to increase the conversion rate) in those applications
where an analog signal is being monitored until some con-
dition becomes true. For example, if the signal is outside a
predetermined range, the full 12-bit conversion result may
not be needed. If so, the conversion can be terminated after
the first n-bits, where n might be as low as 3 or 4. This
results in lower power dissipation in both the converter and
the rest of the system, as they spend more time in the power
down mode.
LAYOUT
For optimum performance, care should be taken with the
physical layout of the ADS7816 circuitry. This is particularly
true if the reference voltage is low and/or the conversion rate
is high. At 200kHz conversion rate, the ADS7816 makes a bit
decision every 312ns. That is, for each subsequent bit deci-
1000
100
10
1
1
TA = 25°C
VCC = VREF = +5V
fCLK = 3.2MHz
10 100
Sample Rate (kHz)
1000
FIGURE 3. Maintaining fCLK at the Highest Possible Rate
Allows Supply Current to Drop Directly with
Sample Rate.
1000
100
10
1
1
TA = 25°C
VCC = VREF = +5V
fCLK = 16 • fSAMPLE
10 100
Sample Rate (kHz)
1000
FIGURE 4. Scaling fCLK Reduces Supply Current Only
Slightly with Sample Rate.
60
TA = 25°C
50 VCC = VREF = +5V
fCLK = 16 • fSAMPLE
40
30
CS LOW
(GND)
20
10
0
1
CS = HIGH (VCC)
10 100
Sample Rate (kHz)
1000
FIGURE 5. Shutdown Current is Considerably Lower with
CS HIGH than when CS is LOW.
®
11 ADS7816
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet ADS7816C.PDF ] | |
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