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PDF ADS7812UB Data sheet ( Hoja de datos )
| Número de pieza | ADS7812UB | |
| Descripción | Low-Power/ Serial 12-Bit Sampling ANALOG-TO-DIGITAL CONVERTER | |
| Fabricantes | Burr-Brown Corporation | |
| Logotipo |  |
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® ADS7812
ADS7812
ADS7812
Low-Power, Serial 12-Bit Sampling
ANALOG-TO-DIGITAL CONVERTER
FEATURES
q 20µs max CONVERSION TIME
q SINGLE +5V SUPPLY OPERATION
q PIN-COMPATIBLE WITH 16-BIT ADS7813
q EASY-TO-USE SERIAL INTERFACE
q 16-PIN 0.3" PLASTIC DIP AND SOIC
q ±0.5LSB max INL AND DNL
q 72dB min SINAD
q USES INTERNAL OR EXTERNAL
REFERENCE
q MULTIPLE INPUT RANGES
q 35mW max POWER DISSIPATION
q NO MISSING CODES
q 50µW POWER DOWN MODE
APPLICATIONS
q DATA ACQUISITION SYSTEMS
q INDUSTRIAL CONTROL
q TEST EQUIPMENT
q DIGITAL SIGNAL PROCESSING
BUSY
DESCRIPTION
The ADS7812 is a low-power, single +5V supply, 12-
bit sampling analog-to-digital converter. It contains a
complete 12-bit capacitor-based SAR A/D with a
sample/hold, clock, reference, and serial data inter-
face.
The converter can be configured for a variety of input
ranges including ±10V, ±5V, 0V to 10V, and 0.5V to
4.5V. A high impedance 0.3V to 2.8V input range is
also available (input impedance > 10MΩ). For most
input ranges, the input voltage can swing to +16.5V or
–16.5V without damage to the converter.
A flexible SPI compatible serial interface allows data
to be synchronized to an internal or external clock.
The ADS7812 is specified at a 40kHz sampling rate
over the –40°C to +85°C temperature range. It is
available in a 16-pin 0.3" plastic DIP or a 16-lead
SOIC package.
PWRD
CONV
CS
Successive Approximation Register and Control Logic
Clock
R1IN
R2IN
R3IN
BUF
CAP
REF
40kΩ(1)
8kΩ(1)
20kΩ(1)
CDAC
Buffer
4kΩ(1)
Internal
+2.5V Ref
Comparator
Serial
Data
Out
EXT/INT
DATACLK
DATA
NOTE: (1) Actual value may vary ±30%.
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
©1997 Burr-Brown Corporation
PDS-11301A
APDrinSted7in8U1.S2.A. March, 1997
®
1 page  
TYPICAL PERFORMANCE CURVES
At TA = +25°C, fS = 40kHz, VS = +5V, ±10V input range, using internal reference, unless otherwise noted.
0
–20
–40
–60
–80
–100
–120
0
FREQUENCY SPECTRUM
(8192 Point FFT; fIN = 980Hz, 0dB)
5 10 15
Frequency (kHz)
20
0
–20
–40
–60
–80
–100
–120
0
FREQUENCY SPECTRUM
(8192 Point FFT; fIN = 9.8kHz, 0dB)
5 10 15
Frequency (kHz)
20
77
76
75
74
73
72
71
–50
SNR AND SINAD vs TEMPERATURE
(fIN = 1kHz, 0dB)
SNR and SINAD
–25 0
25 50 75
Temperature (°C)
100
100
99
98
97
96
95
94
–50
SFDR AND THD vs TEMPERATURE
(fIN = 1kHz, 0dB)
SFDR
THD
–25 0
25 50 75
Temperature (°C)
–100
–99
–98
–97
–96
–95
–94
100
74.0
73.8
73.6
73.4
73.2
73.0
100
SIGNAL-TO-(NOISE + DISTORTION)
vs INPUT FREQUENCY (fIN = 0dB)
1k
Input Signal Frequency (Hz)
10k 20k
2.515
2.510
2.505
2.500
2.495
2.490
2.485
–50
INTERNAL REFERENCE VOLTAGE
vs TEMPERATURE
–25 0
25 50 75
Temperature (°C)
100
®
5 ADS7812
5 Page 
might be possible to use the rising edge of the DATACLK
signal. However, one extra clock period (not shown in
Figures 6, 7, and 8) is needed for the final bit.
The external DATACLK signal must be LOW or CS must
be HIGH prior to BUSY rising (see time t25 in Figures 7 and
8). If this is not observed, the output shift register of the
ADS7812 will not be updated with the conversion result.
Instead, the previous contents of the shift register will
remain and the new result will be lost.
If more than 12 clock cycles are provided to the DATACLK
input, the DATA output will go LOW after the rising edge
of the 13th clock period. The operation of the ADS7812 will
not be affected as long as the timing specifications are met.
Before reading the next three paragraphs, consult the Sensi-
tivity to External Digital Signals section of this data sheet.
This will explain many of the concerns regarding how and
when to apply the external DATACLK signal.
External DATACLK Active After the Conversion
The preferred method of obtaining the conversion result is to
provide the DATACLK signal after the conversion has been
completed and before the next conversion starts—as shown
in Figure 6. Note that the DATACLK signal should be static
before the start of the next conversion. If this is not ob-
served, the DATACLK signal could affect the voltage that
is acquired.
External DATACLK Active During the Next Conversion
Another method of obtaining the conversion result is shown
in Figure 7. Since the output shift register is not updated until
the end of the conversion, the previous result remains valid
during the next conversion. If a fast clock (≥ 2MHz) can be
provided to the ADS7812, the result can be read during time
t2. During this time, the noise from the DATACLK signal is
less likely to affect the conversion result.
CONV
t1
t2
BUSY
DATACLK
DATA
t24
t19
t20
t21
t23
1234
t22
MSB
Bit 10
Bit 9
11 12
Bit 1
LSB
t25
1
MSB
FIGURE 7. Serial Data Timing, External Clock, Clocking During the Next Conversion (EXT/INT HIGH,
CS LOW).
CONV
BUSY
DATACLK
t4
1
2
n
t5
t24
n+1 11 12
t25
DATA
MSB
Bit 10
Bit n
Bit n-1 Bit 1
LSB
FIGURE 8. Serial Data Timing, External Clock, Clocking After the Conversion Completes and During the Next Conversion
(EXT/INT HIGH, CS LOW).
®
11 ADS7812
11 Page | ||
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| PDF Descargar | [ Datasheet ADS7812UB.PDF ] | |
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