PDF ADS5270IPFP Data sheet ( Hoja de datos )

Número de pieza	ADS5270IPFP
Descripción	8-Channel/ 12-Bit/ 40MSPS ADC with Serial LVDS Interface
Fabricantes	Burr-Brown Corporation
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No Preview Available ! ADS5270 SBAS293D − JANUARY 2004 − REVISED MAY 2004 8-Channel, 12-Bit, 40MSPS ADC with Serial LVDS Interface FEATURES D Maximum Sample Rate: 40MSPS D 12-Bit Resolution D No Missing Codes D Power Dissipation: 907mW D CMOS Technology D Simultaneous Sample-and-Hold D 70.5dB SNR at 10MHz IF D Internal and External References D 3.3V Digital/Analog Supply D Serialized LVDS Outputs D Integrated Frame and Synch Patterns D MSB and LSB First Modes D Option to Double LVDS Clock Output Currents D Pin- and Format-Compatible Family D TQFP-80 PowerPAD Package APPLICATIONS D Portable Ultrasound Systems D Tape Drives D Test Equipment D Optical Networking DESCRIPTION or LSB first. The bit coinciding with the rising edge of the 1x clock output is the first bit of the word. Data is to be latched by the receiver on both the rising and falling edges of the 6x clock. The ADS5270 provides internal references, or can optionally be driven with external references. Best performance can be achieved through the internal reference mode. The device is available in a PowerPAD TQFP-80 package and is specified over a −40°C to +85°C operating range. 6X ADCLK ADCLK IN1P IN1N S/H IN2P IN2N S/H IN3P IN3N S/H IN4P IN4N S/H IN5P IN5N S/H PLL 1X ADCLK 12−Bit ADC 12−Bit ADC 12−Bit ADC 12−Bit ADC 12−Bit ADC Serializer Serializer Serializer Serializer Serializer LCLKP LCLKN ADCLKP ADCLKN OUT1P OUT1N OUT2P OUT2N OUT3P OUT3N OUT4P OUT4N OUT5P OUT5N The ADS5270 is a high-performance, 40MSPS, 8-channel, parallel analog-to-digital converter (ADC). Internal references are provided, simplifying system design requirements. Low power consumption allows for the highest of system integration densities. Serial LVDS (low-voltage differential signaling) outputs reduce the number of interface lines and package size. An integrated phase lock loop multiplies the incoming ADC sampling clock by a factor of 12. This 12x clock is used in the process of serializing the data output from each channel. The 12x clock is also used to generate a 1x and a 6x clock, both of which are transmitted as LVDS clock outputs. The 6x clock is denoted by the differential pair LCLKP and LCLKN, while the 1x clock is denoted by ADCLKP and ADCLKN. The word output of each ADC channel can be transmitted either as MSB IN6P IN6N S/H IN7P IN7N S/H IN8P IN8N S/H 12−Bit ADC 12−Bit ADC 12−Bit ADC Serializer Serializer Serializer Reference Registers Control INT/EXT OUT6P OUT6N OUT7P OUT7N OUT8P OUT8N Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a registered trademark of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright  2004, Texas Instruments Incorporated www.ti.com 1 page ADS5270 www.ti.com SBAS293D − JANUARY 2004 − REVISED MAY 2004 SWITCHING CHARACTERISTICS TMIN = −40°C, TMAX = +85°C. Typical values are at TA = 25°C, clock frequency = maximum specified, 50% clock duty cycle, AVDD = 3.3V, LVDD = 3.3V, −1dBFS, internal voltage reference, and LVDS buffer current at 3.5mA per channel, unless otherwise noted. ADS5270 PARAMETER SWITCHING SPECIFICATIONS tD(A) tSAMPLE Aperture Delay Aperture Jitter (uncertainty) tD(pipeline) Latency tPROP Propagation Delay CONDITIONS MIN TYP MAX UNITS 25 50 ns 2.5 ns 1 ps 6.5 cycles 5 ns SERIAL INTERFACE TIMING Data is shifted in MSB first. ADCLK Outputs change on next rising clock edge after CS goes high. CS SCLK Start Sequence t1 t2 t3 SDATA MSB t4 t5 PARAMETER t1 t2 t3 t4 t5 D6 D5 D4 DESCRIPTION Serial CLK Period Serial CLK High Time Serial CLK Low Time Minimum Data Setup Time Minimum Data Hold Time Data latched on each rising edge of SCLK. D3 D2 D1 MIN TYP 50 25 25 5 5 D0 MAX UNIT ns ns ns ns ns 5 5 Page ADS5270 www.ti.com SBAS293D − JANUARY 2004 − REVISED MAY 2004 TYPICAL CHARACTERISTICS (continued) Typical values are at TA = 25°C, clock frequency = maximum specified, 50% clock duty cycle, AVDD = 3.3V, LVDD = 3.3V, −1dBFS, ISET = 56kΩ, internal voltage reference, and LVDS buffer current at 3.5mA per channel, unless otherwise noted. INTEGRAL NONLINEARITY 2.0 fIN = 5MHz 1.5 1.0 0.5 0 −0.5 −1.0 −1.5 −2.0 0 512 1024 1536 2048 2560 3072 3584 4096 Code SWEPT INPUT POWER 100 90 80 SNR (dBFS) 70 60 50 SFDR (dBc) 40 30 20 SNR (dBc) 10 0 −70 −60 −50 −40 −30 −20 Input Amplitude (A) fIN = 5MHz −10 0 SWEPT INPUT POWER 100 90 80 SNR (dBFS) 70 60 50 SFDR (dBc) 40 30 SNR (dBc) 20 10 fIN = 10MHz 0 −70 −60 −50 −40 −30 −20 −10 0 Input Amplitude (A) 90 85 80 75 70 65 60 55 20 DYNAMIC PERFORMANCE vs DUTY CYCLE SFDR SNR fIN = 5MHz 30 40 50 60 70 80 Duty Cycle (%) DYNAMIC PERFORMANCE vs INPUT FREQUENCY 95 90 SFDR 85 80 75 70 SNR 65 60 55 5 10 15 20 25 30 35 40 45 50 Input Frequency (MHz) DYNAMIC PERFORMANCE vs CLOCK FREQUENCY 90 SFDR 85 80 75 SNR 70 SINAD 65 60 fIN = 5MHz 55 20 25 30 35 Clock Frequency (MHz) 40 45 11 11 Page

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