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PDF ADS1224IPWR Data sheet ( Hoja de datos )
| Número de pieza | ADS1224IPWR | |
| Descripción | 24-Bit Analog-to-Digital Converter with 4-Channel Differential Input Multiplexer | |
| Fabricantes | Burr-Brown Corporation | |
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ADS1224
SBAS286A − JUNE 2003 − REVISED MARCH 2004
24ĆBit AnalogĆtoĆDigital Converter
with 4ĆChannel Differential Input Multiplexer
FEATURES
D 240SPS Data Rate with 4MHz Clock
D 20-Bit Effective Resolution
D Input Multiplexer with Four Differential
Channels
D Pin-Selectable, High-Impedance Input Buffer
D ±5V Differential Input Range
D 0.0003% INL (typ), 0.0015% INL (max)
D Self-Calibrating
D Simple 2-Wire Serial Interface
D On-Chip Temperature Sensor
D Single Conversions with Standby Mode
D Low Current Consumption: 300µA
D Analog Supply: 2.7V to 5.5V
D Digital Supply: 2.7V to 5.5V
APPLICATIONS
D Hand-Held Instrumentation
D Portable Medical Equipment
D Industrial Process Control
D Weigh Scales
DESCRIPTION
The ADS1224 is a 4-channel, 24-bit, delta-sigma ana-
log-to-digital (A/D) converter. It offers excellent perfor-
mance and low power in a TSSOP-20 package. The
ADS1224 is well-suited for demanding, high-resolution
measurements, especially in portable systems and oth-
er space-saving and power-constrained applications.
A delta-sigma modulator and digital filter form the basis
of the A/D converter. The analog modulator has a ±5V
differential input range. An input multiplexer (mux) is
used to select between four separate differential input
channels. A buffer can be selected to increase the input
impedance of the measurement.
A simple, 2-wire serial interface provides all the
necessary control. Data retrieval, self-calibration, and
Standby mode are handled with a few simple
waveforms. When only single conversions are needed,
the ADS1224 can be quickly shut down (Standby mode)
while idle between measurements to dramatically
reduce the overall power consumption. Multiple
ADS1224s can be connected together to create a
synchronously sampling multichannel measurement
system. The ADS1224 is designed to easily connect to
microcontrollers, such as the MSP430.
The ADS1224 supports 2.7V to 5.5V analog supplies
and 2.7V to 5.5V digital supplies. Power is typically less
than 1mW in 3V operation and less than 1µW during
Standby mode.
TEMPEN
AVDD
VREFP VREFN DVDD
AINP1
AINN1
AINP2
AINN2
Mux Buffer
AINP3
AINN3
AINP4
AINN4
CLK
∆Σ
Modulator
Digital Filter
and
Serial Interface
SCLK
DRDY/DOUT
MUX0 MUX1 BUFEN
GND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
Copyright 2003−2004, Texas Instruments Incorporated
www.ti.com
1 page  
www.ti.com
PIN ASSIGNMENTS
ADS1224
SBAS286A − JUNE 2003 − REVISED MARCH 2004
PW PACKAGE
TSSOP
(TOP VIEW)
DVDD 1
SCLK 2
CLK 3
DRDY/DOUT 4
MUX0 5
MUX1 6
TEMPEN 7
BUFEN 8
AINP4 9
AINN4 10
ADS1224
20 AVDD
19 VREFP
18 VREFN
17 GND
16 AINN1
15 AINP1
14 AINN2
13 AINP2
12 AINN3
11 AINP3
TERMINAL
NAME
DVDD
NO.
1
SCLK
2
CLK 3
DRDY/DOUT
4
MUX0
MUX1
TEMPEN
BUFEN
AINP4
AINN4
AINP3
AINN3
AINP2
AINN2
AINP1
AINN1
GND
VREFN
VREFP
AVDD
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Terminal Functions
I/O
Digital
Digital input
Digital input
Digital Ouput
Digital input
Digital input
Digital input
Digital input
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input
Analog/Digital
Analog input
Analog input
Analog
Digital power supply
DESCRIPTION
Serial clock input
System clock input
Dual-purpose output:
Data Ready: indicates valid data by going low.
Data Output: outputs data, MSB first, on the rising edge of SCLK.
Selects analog input of mux, bit 0
Selects analog input of mux, bit 1
Selects temperature sensor input from mux
Enables input buffer
Analog channel 4 positive input
Analog channel 4 negative input
Analog channel 3 positive input
Analog channel 3 negative input
Analog channel 2 positive input
Analog channel 2 negative input
Analog channel 1 positive input
Analog channel 1 negative input
Analog and digital ground
Negative reference input
Positive reference input
Analog power supply
5
5 Page 
ADS1224
www.ti.com
allowable voltage range on VREFP and VREFN during
self or self gain calibration as the reference pins must
remain within the specified input range of the buffer in
order to establish proper gain calibration.
For best performance, VREF should be AVDD/2, but it can
be raised as high as AVDD. When VREF exceeds
AVDD/2, it is not possible to reach the full-scale digital
output value corresponding to ±2VREF, since this requires
the analog inputs to exceed the power supplies. For
example, if VREF = AVDD = 5V, the positive full-scale
signal is 10V. The maximum positive input signal that can
be supplied before the ESD diodes turn on is when AINP
= 5.1V and AINN = –0.1V, resulting in VIN = 5.2V.
Therefore, it is not possible to reach the positive (or
negative) full-scale readings in this configuration. The
digital output codes are limited to approximately one half
of the entire range. For best performance, bypass the
voltage reference inputs with a 0.1µF capacitor between
VREFP and VREFN. Place the capacitor as close as
possible to the pins.
CLOCK INPUT (CLK)
This digital input supplies the system clock to the
ADS1224. The CLK frequency can be increased to
speed up the data rate. CLK must be left running during
normal operation. It may be turned off during Standby
mode to save power, but this is not required. The CLK
input may be driven with 5V logic, regardless of the
DVDD or AVDD voltage.
Minimize the overshoot and undershoot on CLK for the
best analog performance. A small resistor in series with
CLK (10Ω to 100Ω) can often help. CLK can be
generated from a number of sources including
standalone crystal oscillators and microcontrollers.
DATA READY/DATA OUTPUT (DRDY/DOUT)
This digital output pin serves two purposes. First, it
indicates when new data is ready by going LOW.
Afterwards, on the first rising edge of SCLK, the
DRDY/DOUT pin changes function and begins
outputting the conversion data, most significant bit
(MSB) first. Data is shifted out on each subsequent
SCLK rising edge. After all 24 bits have been retrieved,
SBAS286A − JUNE 2003 − REVISED MARCH 2004
the pin can be forced high with an additional SCLK. It will
then stay high until new data is ready. This is useful
when polling on the status of DRDY/DOUT to determine
when to begin data retrieval.
SERIAL CLOCK INPUT (SCLK)
This digital input shifts serial data out with each rising
edge. As with CLK, this input may be driven with 5V
logic regardless of the DVDD or AVDD voltage. There
is hysteresis built into this input, but care should still be
taken to ensure a clean signal. Glitches or slow-rising
signals can cause unwanted additional shifting. For this
reason, it is best to make sure the rise-and-fall times of
SCLK are less than 50ns.
FREQUENCY RESPONSE
The ADS1224 frequency response for fCLK = 2MHz is
shown in Figure 20. The frequency response repeats at
multiples of the modulator sampling frequency of
62.5kHz. The overall response is that of a low-pass filter
with a −3db cutoff frequency of 31.5Hz. As shown, the
ADS1224 does a good job attenuating out to 60kHz. For
the best resolution, limit the input bandwidth to less than
this value to keep higher frequency noise from affecting
performance. Often, a simple RC filter on the ADS1224
analog inputs is all that is needed.
0
−20
−40
−60
−80
−100
0
31250
Input Frequency (Hz)
62500
Figure 20. Frequency Response
11
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet ADS1224IPWR.PDF ] | |
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