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PDF ADS1222IPWR Data sheet ( Hoja de datos )
| Número de pieza | ADS1222IPWR | |
| Descripción | 24 BIT ANALOG TO DIGITAL CONVERTER WITH 2-CHANNEL DIFFERENTIAL INPUT MULTIPLEXER | |
| Fabricantes | Burr-Brown Corporation | |
| Logotipo |  |
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ADS1222
SBAS314A − APRIL 2004 − REVISED SEPTEMBER 2004
24ĆBit AnalogĆtoĆDigital Converter
with 2ĆChannel Differential Input Multiplexer
FEATURES
D 240SPS Data Rate with 4MHz Clock
D 20-Bit Effective Resolution
D Input Multiplexer with Two Differential
Channels
D Pin-Selectable, High-Impedance Input Buffer
D ±5V Differential Input Range
D 0.0003% INL (typ), 0.0015% INL (max)
D Self-Calibrating
D Simple 2-Wire Serial Interface
D On-Chip Temperature Sensor
D Single Conversions with Standby Mode
D Low Current Consumption: 300µA
D Analog Supply: 2.7V to 5.5V
APPLICATIONS
D Hand-Held Instrumentation
D Portable Medical Equipment
D Industrial Process Control
D Weigh Scales
DESCRIPTION
The ADS1222 is a 2-channel, 24-bit, delta-sigma ana-
log-to-digital (A/D) converter. It offers excellent perfor-
mance and low power in a TSSOP-14 package. The
ADS1222 is well-suited for demanding, high-resolution
measurements, especially in portable systems and oth-
er space-saving and power-constrained applications.
A delta-sigma modulator and digital filter form the basis
of the A/D converter. The analog modulator has a ±5V
differential input range. An input multiplexer (mux) is
used to select between two separate differential input
channels. A buffer can be selected to increase the input
impedance of the measurement.
A simple, 2-wire serial interface provides all the
necessary control. Data retrieval, self-calibration, and
Standby mode are handled with a few simple
waveforms. When only single conversions are needed,
the ADS1222 can be quickly shut down (Standby mode)
while idle between measurements to dramatically
reduce the overall power consumption. Multiple
ADS1222s can be connected together to create a
synchronously sampling multichannel measurement
system. The ADS1222 is designed to easily connect to
microcontrollers, such as the MSP430.
The ADS1222 supports 2.7V to 5.5V supplies. Power
is typically less than 1mW in 3V operation and less than
1µW during Standby mode.
TEMPEN
AINP1
AINN1
AINP2
AINN2
Mux
VDD
VREFP VREFN
Buffer
CLK
∆Σ
Modulator
Digital Filter
and
Serial Interface
SCLK
DRDY/DOUT
MUX
BUFEN
GND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
Copyright 2004, Texas Instruments Incorporated
www.ti.com
1 page  
www.ti.com
PIN ASSIGNMENTS
ADS1222
SBAS314A − APRIL 2004 − REVISED SEPTEMBER 2004
PW PACKAGE
TSSOP-14
(TOP VIEW)
VDD 1
SCLK 2
CLK 3
DRDY/DOUT 4
MUX 5
TEMPEN 6
BUFEN 7
ADS1222
14 VREFP
13 VREFN
12 GND
11 AINN1
10 AINP1
9 AINN2
8 AINP2
TERMINAL
NAME
VDD
NO.
1
SCLK
2
CLK 3
DRDY/DOUT
4
MUX
TEMPEN
BUFEN
AINP2
AINN2
AINP1
AINN1
GND
VREFN
VREFP
5
6
7
8
9
10
11
12
13
14
Terminal Functions
I/O
Analog/Digital
Digital input
Digital input
Digital Output
Digital input
Digital input
Digital input
Analog input
Analog input
Analog input
Analog input
Analog/Digital
Analog input
Analog input
Analog and digital power supply
DESCRIPTION
Serial clock input
System clock input
Dual-purpose output:
Data ready: indicates valid data by going low.
Data output: outputs data, MSB first, on the rising edge of SCLK.
Selects analog input of mux
Selects temperature sensor input from mux
Enables input buffer
Analog channel 2 positive input
Analog channel 2 negative input
Analog channel 1 positive input
Analog channel 1 negative input
Analog and digital ground
Negative reference input
Positive reference input
5
5 Page 
ADS1222
www.ti.com
the buffer will limit the allowable voltage range on
VREFP and VREFN during self or self gain calibration
as the reference pins must remain within the specified
input range of the buffer in order to establish proper gain
calibration.
For best performance, VREF should be VDD/2, but it can
be raised as high as VDD. When VREF exceeds VDD/2,
it is not possible to reach the full-scale digital output
value corresponding to ±2VREF, since this requires the
analog inputs to exceed the power supplies. For
example, if VREF = VDD = 5V, the positive full-scale
signal is 10V. The maximum positive input signal that
can be supplied before the ESD diodes turn on is when
AINP = 5.1V and AINN = –0.1V, resulting in VIN = 5.2V.
Therefore, it is not possible to reach the positive (or
negative) full-scale readings in this configuration. The
digital output codes are limited to approximately one
half of the entire range. For best performance, bypass
the voltage reference inputs with a 0.1µF capacitor
between VREFP and VREFN. Place the capacitor as
close as possible to the pins.
CLOCK INPUT (CLK)
This digital input supplies the system clock to the
ADS1222. The CLK frequency can be increased to
speed up the data rate. CLK must be left running during
normal operation. It may be turned off during Standby
mode to save power, but this is not required. The CLK
input may be driven with 5V logic, regardless of the VDD
voltage.
Minimize the overshoot and undershoot on CLK for the
best analog performance. A small resistor in series with
CLK (10Ω to 100Ω) can often help. CLK can be
generated from a number of sources including
standalone crystal oscillators and microcontrollers.
DATA READY/DATA OUTPUT (DRDY/DOUT)
This digital output pin serves two purposes. First, it
indicates when new data is ready by going LOW.
Afterwards, on the first rising edge of SCLK, the
DRDY/DOUT pin changes function and begins to
output the conversion data, most significant bit (MSB)
first. Data is shifted out on each subsequent SCLK
rising edge. After all 24 bits have been retrieved, the pin
SBAS314A − APRIL 2004 − REVISED SEPTEMBER 2004
can be forced high with an additional SCLK. It will then
stay high until new data is ready. This is useful when
polling on the status of DRDY/DOUT to determine when
to begin data retrieval.
SERIAL CLOCK INPUT (SCLK)
This digital input shifts serial data out with each rising
edge. As with CLK, this input may be driven with 5V
logic regardless of the VDD voltage. There is hysteresis
built into this input, but care should still be taken to
ensure a clean signal. Glitches or slow-rising signals
can cause unwanted additional shifting. For this reason,
it is best to make sure the rise-and-fall times of SCLK
are less than 50ns.
FREQUENCY RESPONSE
The ADS1222 frequency response for fCLK = 2MHz is
shown in Figure 20. The frequency response repeats at
multiples of the modulator sampling frequency of
62.5kHz. The overall response is that of a low-pass filter
with a −3db cutoff frequency of 31.5Hz. As shown, the
ADS1222 does a good job attenuating out to 60kHz. For
the best resolution, limit the input bandwidth to less than
this value to keep higher frequency noise from affecting
performance. Often, a simple RC filter on the ADS1222
analog inputs is all that is needed.
0
−20
−40
−60
−80
−100
0
31250
Input Frequency (Hz)
62500
Figure 20. Frequency Response
11
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| PDF Descargar | [ Datasheet ADS1222IPWR.PDF ] | |
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