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PDF ADV7196A Data sheet ( Hoja de datos )
| Número de pieza | ADV7196A | |
| Descripción | Multiformat Progressive Scan/HDTV Encoder with Three 11-Bit DACs/ 10-Bit Data Input/ and Macrovision | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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a
Multiformat Progressive Scan/HDTV
Encoder with Three 11-Bit DACs,
10-Bit Data Input, and Macrovision
ADV7196A
FEATURES
INPUT FORMATS
YCrCb in 2 ؋ 10-Bit (4:2:2) or 3 ؋ 10-Bit (4:4:4) Format
Compliant to SMPTE-293M (525p), ITU-R.BT1358
(625p), SMPTE274M (1080i), SMPTE296M (720p) and
Any Other High Definition Standard Using Async
Timing Mode
RGB in 3 ؋ 10 Bit (4:4:4) Format
OUTPUT FORMATS
YPrPb Progressive Scan (EIA-770.1, EIA-770.2)
YPrPb HDTV (EIA-770.3)
RGB Levels Compliant to RS-170 and RS-343A
11-Bit and Sync (DAC A)
11-Bit DACs (DAC B, DAC C)
PROGRAMMABLE FEATURES
Internal Test Pattern Generator with Color Control
Y/C Delay (؎)
Gamma Correction
Individual DAC On/Off Control
54 MHz Output (2؋ Oversampling)
Sharpness Filter with Programmable Gain/Attenuation
Programmable Adaptive Filter Control
Undershoot Limiter
I2C® Filter
VBI Open Control
Macrovision Rev. 1.0 (525p)
CGMS-A (525p)
2-Wire Serial MPU Interface
Single Supply 3.3 V Operation
52-MQFP Package
APPLICATIONS
Progressive Scan/HDTV Display Devices
DVD Players
MPEG 2 at 81 MHz
Progressive Scan/HDTV Projection Systems
Digital Video Systems
High Resolution Color Graphics
Image Processing/Instrumentation
Digital Radio Modulation/Video Signal Reconstruction
GENERAL DESCRIPTION
The ADV7196A is a triple high-speed, digital-to-analog encoder
on a single monolithic chip. It consists of three high-speed video
D/A converters with TTL-compatible inputs.
Y0–Y9
Cr0–Cr9
Cb0–Cb9
CLKIN
HORIZONTAL
SYNC
VERTICAL
SYNC
BLANKING
RESET
FUNCTIONAL BLOCK DIAGRAM
SHARPNESS
FILTER CONTROL
AND
ADAPTIVE
FILTER CONTROL
CGMS
MACROVISION
TEST PATTERN
GENERATOR
AND
DELAY
AND
GAMMA
CORRECTION
CHROMA
4:2:2
TO
4:4:4
(SSAF)
CHROMA
4:2:2
TO
4:4:4
(SSAF)
LUMA
SSAF
2؋ INTER-
POLATION
ADV7196A
11-BIT+
SYNC
DAC
11-BIT
DAC
11-BIT
DAC
TIMING
GENERATOR
SYNC
GENERATOR
I2C MPU
PORT
DAC CONTROL
BLOCK
DAC A (Y)
DAC B
DAC C
VREF
RESET
COMP
The ADV7196A has three separate 10-bit-wide input ports which
accept data in 4:4:4 10-bit YCrCb or RGB or 4:2:2 10-bit YCrCb.
This data is accepted in progressive scan format at 27 MHz or
HDTV format at 74.25 MHz or 74.1758 MHz. For any other
high-definition standard but SMPTE 293M, ITU-R BT.1358,
SMPTE274M or SMPTE296M the Async Timing Mode can be
used to input data to the ADV7196A. For all standards, external
horizontal, vertical, and blanking signals or EAV/SAV codes control
the insertion of appropriate synchronization signals into the digital
data stream and therefore the output signals.
The ADV7196A outputs analog YPrPb progressive scan format
complying to EIA-770.1, EIA-770.2; YPrPb HDTV complying
to EIA-770.3; RGB complying to RS-170/RS-343A.
The ADV7196A requires a single 3.3 V power supply, an
optional external 1.235 V reference and a 27 MHz clock in
Progressive Scan Mode or a 74.25 MHz (or 74.1758 MHz)
clock in HDTV mode.
In Progressive Scan Mode, a sharpness filter with programmable
gain allows high-frequency enhancement on the luminance signal.
Programmable Adaptive Filter Control, which may be used, allows
removal of ringing on the incoming Y data. The ADV7196A
supports CGMS-A data control generation and the Macrovision
Anticopy algorithm in 525p mode.
The ADV7196A is packaged in a 52-lead MQFP package.
I2C is a registered trademark of Philips Corporation.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
1 page  
ADV7196A
3.3 V TIMING–SPECIFICATIONS (VAA = 3.15 V to 3.45 V, VREF = 1.235 V, RSET = 2470 ⍀, RLOAD = 300 ⍀. All specifications
TMIN to TMAX (0؇C to 70؇C) unless otherwise noted.)
Parameter
MPU PORT1
SCLOCK Frequency
SCLOCK High Pulsewidth, t1
SCLOCK Low Pulsewidth, t2
Hold Time (Start Condition), t3
Setup Time (Start Condition), t4
Data Setup Time, t5
SDATA, SCLOCK Rise Time, t6
SDATA, SCLOCK Fall Time, t7
Setup Time (Stop Condition), t8
Reset Low Time
Min Typ
0
0.6
1.3
0.6
0.6
100
0.6
100
Max Unit
400 kHz
µs
µs
µs
µs
ns
300 ns
300 ns
µs
ns
Conditions
After This Period the 1st Clock Is Generated
Relevant for Repeated Start Condition
ANALOG OUTPUTS
Analog Output Delay2
Analog Output Skew
CLOCK CONTROL AND PIXEL PORT3
fCLK
fCLK
fCLK
Clock High Time t9
Clock Low Time t10
Data Setup Time t11
Data Hold Time t12
Control Setup Time t11
Control Hold Time t12
Pipeline Delay
Pipeline Delay
5.0
5.0
2.0
4.5
7.0
4.0
16
29
10
0.5
1.5
2.0
ns
ns
27
74.25
81
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
Clock Cycles
Clock Cycles
Progressive Scan Mode
HDTV Mode
Async Timing Mode and 1× Interpolation
For 4:4:4 Pixel Input Format at 1× Oversampling
For 4:4:4 or 4:2:2 Pixel Input Format at 2×
Oversampling
NOTES
1Guaranteed by characterization.
2Output delay measured from 50% point of the rising edge of CLOCK to the 50% point of DAC output full-scale transition.
3Data: Cb/Cr [9–0], Cr [9–0], Y [9:0]
Control: HSYNC/SYNC, VSYNC/TSYNC, DV
Specifications subject to change without notice.
REV. 0
–5–
5 Page 
Input/Output Configuration
Table I shows possible input/output configurations when using
the ADV7196A.
Table I.
Input Format
YCrCb Progressive Scan
4:2:2
4:4:4
YCrCb HDTV
4:2:2
4:4:4
RGB Progressive Scan
4:4:4
RGB HDTV
4:4:4
Async Timing Mode
All Inputs
Output
2×
1× or 2×
1×
1×
2×
1×
1×
10
0
–10
–20
–30
–40
–50
–60
–70
–80
0
5 10 15 20 25 30
Figure 8. 2× Interpolation Filter – Y-Channel
10
0
–10
–20
–30
–40
–50
–60
–70
–80
0
5 10 15 20 25 30
Figure 9. Interpolation Filter – CrCb Channels for 4:2:2
Input Data
ADV7196A
10
0
–10
–20
–30
–40
–50
–60
–70
–80
0
5 10 15 20 25 30
Figure 10. Interpolation Filter – CrCb Channels for 4:4:4
Input Data
MPU PORT DESCRIPTION
The ADV7196A support a 2-wire serial (I2C-compatible) micro-
processor bus driving multiple peripherals. Two inputs, Serial Data
(SDA) and Serial Clock (SCL), carry information between any
device connected to the bus. Each slave device is recognized by a
unique address. The ADV7196A has four possible slave addresses
for both read and write operations. These are unique addresses
for each device and illustrated in Figure 11. The LSB sets either
a read or write operation. Logic Level “1” corresponds to a read
operation while Logic Level “0” corresponds to a write opera-
tion. A1 is set by setting the ALSB pin of the ADV7196A to Logic
Level “0” or Logic Level “1.” When ALSB is set to “0,” there is
greater input bandwidth on the I2C lines, which allows high-
speed data transfers on this bus. When ALSB is set to “1,” there
is reduced input bandwidth on the I2C lines, which means that
pulses of less than 50 ns will not pass into the I2C internal control-
ler. This mode is recommended for noisy systems.
1 1 0 1 0 1 A1 X
ADDRESS
CONTROL
SET UP BY
ALSB
READ / W RITE
CONTROL
0 WRITE
1 READ
Figure 11. Slave Address
To control the various devices on the bus the following protocol
must be followed. First the master initiates a data transfer by
establishing a Start condition, defined by a high-to-low transi-
tion on SDA while SCL remains high. This indicates that an
address/data stream will follow. All peripherals respond to the
Start condition and shift the next eight bits (7-bit address + R/W
bit). The bits are transferred from MSB down to LSB. The
peripheral that recognizes the transmitted address responds by
pulling the data line low during the ninth clock pulse. This is
known as an acknowledge bit. All other devices withdraw from
the bus at this point and maintain an idle condition. The idle
condition is where the device monitors the SDA and SCL lines
waiting for the Start condition and the correct transmitted address.
The R/W bit determines the direction of the data.
REV. 0
–11–
11 Page | ||
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