ADV7195 Datasheet PDF - Analog Devices
| Part Number | ADV7195 | |
| Description | Multiformat Progressive Scan/HDTV Encoder | |
| Manufacturers | Analog Devices | |
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a
Multiformat Progressive Scan/HDTV
Encoder with Three 11-Bit DACs
and 10-Bit Data Input
ADV7195
FEATURES
INPUT FORMATS
YCrCb in 2 ؋ 10-Bit (4:2:2) or 3 ؋ 10-Bit (4:4:4) Format-
Compliant to SMPTE-293M (525p), ITU-R.BT1358
(625p), SMPTE274M (1080i), SMPTE296M (720p)
and Any Other High-Definition Standard Using
Async Timing Mode
RGB in 3 ؋ 10 Bit (4:4:4) Format
OUTPUT FORMATS
YPrPb Progressive Scan (EIA-770.1, EIA-770.2)
YPrPb HDTV (EIA-770.3)
RGB Levels Compliant to RS-170 and RS-343A
11-Bit + Sync (DAC A)
11-Bit DACs (DAC B, DAC C)
PROGRAMMABLE FEATURES
Internal Test Pattern Generator with Color Control
Y/C Delay (؎)
Gamma Correction
Individual DAC On/Off Control
54 MHz Output (2؋ Oversampling)
Sharpness Filter with Programmable Gain/Attenuation
Programmable Adaptive Filter Control
Undershoot Limiter
VBI Open Control
I2C® Filter
CGMS-A (525p)
2-Wire Serial MPU Interface
Single Supply 3.3 V Operation
52-MQFP Package
APPLICATIONS
Progressive Scan/HDTV Display Devices
MPEG at 81 MHz
Progressive Scan/HDTV Projection Systems
Digital Video Systems
High Resolution Color Graphics
Image Processing/Instrumentation
Digital Radio Modulation/Video Signal Reconstruction
GENERAL DESCRIPTION
The ADV7195 is a triple high-speed, digital-to-analog encoder
on a single monolithic chip. It consists of three high-speed video
D/A converters with TTL-compatible inputs.
FUNCTIONAL BLOCK DIAGRAM
Y0–Y9
Cr0–Cr9
Cb0–Cb9
CLKIN
HORIZONTAL
SYNC
VERTICAL
SYNC
BLANKING
RESET
SHARPNESS
FILTER CONTROL
AND
ADAPTIVE
FILTER CONTROL
CGMS
MACROVISION
TEST PATTERN
GENERATOR
AND
DELAY
AND
GAMMA
CORRECTION
CHROMA
4:2:2
TO
4:4:4
(SSAF)
CHROMA
4:2:2
TO
4:4:4
(SSAF)
LUMA
SSAF
2؋ INTER-
POLATION
ADV7195
11-BIT+
SYNC
DAC
11-BIT
DAC
11-BIT
DAC
TIMING
GENERATOR
SYNC
GENERATOR
I2C MPU
PORT
DAC CONTROL
BLOCK
DAC A (Y)
DAC B
DAC C
VREF
RESET
COMP
The ADV7195 has three separate 10-bit-wide input ports that
accept data in 4:4:4 10-bit YCrCb or RGB or 4:2:2 10-bit YCrCb.
This data is accepted in progressive scan format at 27 MHz or
HDTV format at 74.25 MHz or 74.1758 MHz. For any other
high-definition standard but SMPTE293M, ITU-R BT.1358,
SMPTE274M or SMPTE296M the Async Timing Mode can
be used to input data to the ADV7195. For all standards, exter-
nal horizontal, vertical, and blanking signals or EAV/SAV codes
control the insertion of appropriate synchronization signals into
the digital data stream and therefore the output signals.
The ADV7195 outputs analog YPrPb progressive scan format
complying to EIA-770.1, EIA-770.2; YPrPb HDTV complying
to EIA-770.3; RGB complying to RS-170/RS-343A.
The ADV7195 requires a single 3.3 V power supply, an
optional external 1.235 V reference and a 27 MHz clock in
Progressive Scan Mode or a 74.25 MHz (or 74.1758 MHz)
clock in HDTV mode.
In Progressive Scan Mode, a sharpness filter with programmable
gain allows high-frequency enhancement on the luminance signal.
Programmable Adaptive Filter Control, which may be used,
allows removal of ringing on the incoming Y data. The ADV7195
supports CGMS-A data control generation.
The ADV7195 is packaged in a 52-lead MQFP package.
I2C is a registered trademark of Philips Corporation.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002
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ADV7195
3.3 V TIMING–SPECIFICATIONS (VAA = 3.15 V to 3.45 V, VREF = 1.235 V, RSET = 2470 ⍀, RLOAD = 300 ⍀. All specifications
TMIN to TMAX [0؇C to 70؇C] unless otherwise noted.)
Parameter
Min Typ Max Unit
Conditions
MPU PORT1
SCLOCK Frequency
SCLOCK High Pulsewidth, t1
SCLOCK Low Pulsewidth, t2
Hold Time (Start Condition), t3
Setup Time (Start Condition), t4
Data Setup Time, t5
SDATA, SCLOCK Rise Time, t6
SDATA, SCLOCK Fall Time, t7
Setup Time (Stop Condition), t8
RESET Low Time
0
0.6
1.3
0.6
0.6
100
0.6
100
400 kHz
µs
µs
µs
µs
ns
300 ns
300 ns
µs
ns
After this Period the 1st Clock Is Generated
Relevant for Repeated Start Condition
ANALOG OUTPUTS
Analog Output Delay, t62
Analog Output Skew
10 ns
0.5 ns
CLOCK CONTROL AND PIXEL PORT3
fCLK
Clock High Time, t9
Clock Low Time, t10
Data Setup Time, t11
Data Hold Time, t12
Control Setup Time, t11
Control Hold Time, t12
Pipeline Delay
Pipeline Delay
5.0
5.0
2.0
4.5
7.0
4.0
16
29
27
74.25
81
21.5
22.0
3.4
3.2
3.4
3.2
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
Clock Cycles
Clock Cycles
Progressive Scan Mode
HDTV Mode
ASYNC Timing Mode and 1× Interpolation
For 4:4:4 Pixel Input Format at 1× Oversampling
For 4:4:4 or 4:2:2 Pixel Input Format at
2× Oversampling
NOTES
1Guaranteed by characterization.
2Output delay measured from 50% point of rising edge of CLOCK to the 50% point of DAC output full-scale transition.
3Data: Cb/Cr(9–0), Cr(9–0), Y(9–0); Control: HSYNC/SYNC, VSYNC/TSYNC, DV.
Specifications subject to change without notice.
REV. A
–5–
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